The actual level required to take the ethernet switch out of reset is
low, not high.
BUG=chrome-os-partner:31780
TEST=with this patch applied, when proto0.2 boots, the ethernet
switch's LED blink once, as was the case with proto0.
Change-Id: If4004ac5c2dc837270d4cb840d96ce92021d231e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9fa69d22de901cd0843948de0f95a66a2aa99353
Original-Change-Id: I81eeb73b85cf113709b6d4ac3aa7639a40fa6719
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/217416
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9121
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The proto0.2 hardware connects gpio26 (sw reset) to the ethernet
switch reset pit. The output stays low (or high-z) after power up,
which holds the switch in reset. Deassert the signal at startup on
hardware rev 1 and later.
BUG=chrome-os-partner:31780
TEST=with this patch applied, when proto0.2 boots, the ethernet
switch's LED blink once, as was the case with proto0.
Change-Id: I4c5a0cc499563a33aa7d29be7767d0ec5d93c20f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6788962172c6e29e193fa3e85ca79cb83a96e154
Original-Change-Id: I81b3dccb1d1d43c5c1e6dcb5400af8eed6dee870
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/217087
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9120
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The proto0 storm hardware has the TPM reset line wired to the SOC GPIO22
pin instead of the system reset. This causes all kind of TPM behavior
problems and requires frequent power cycles. Adding explicit TPM reset
makes all those problems go away.
BUG=chrome-os-partner:30705, chrome-os-partner:30829
TEST=tried resetting proto0 at different moments during boot up - the
TPM does not fail anymore.
Change-Id: Idfa16e6e868336f38861edeb75703fff3f35172c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d5e07815c227089b7f266ba5329812bf309b87e6
Original-Change-Id: Ia877fcd9efaf3ba12c8fe8c2958bd81c4bf22799
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/211497
Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9118
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Storm provides three real and two fake gpios. To keep things simple,
define them all as active low and provide appropriate values for the
fake ones.
BUG=chrome-os-partner:30705
TEST=with the appropriate depthcharge change booted proto0, observed
appropriate behavior following the dev switch setting
Change-Id: I248b90ee06d226a223b6fc0993f209acdd58c77d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d48d1dcc88df0c1bd4c50f14dd2e7cd1dd4fba5d
Original-Change-Id: Icb7fb55949fa97ead9d19f0da76392ee63bbb5b8
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210922
Reviewed-on: http://review.coreboot.org/9117
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add implementation of the GPIO API defined in src/include/gpiolib.h.
Also, clean up the GPIO driver, make it use pointers instead of
integers for register address.
This requires a touch in the SPI driver, where the CS GPIO is toggled
and in the board function where it enables USB interface.
BUG=chrome-os-partner:30489
TEST=tested with the following patches, observed proto0 properly read
the board ID.
Original-Change-Id: I0962947c6bb32a854ca300752d259a48e9e7b4eb
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210115
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit e951f735001509d135cc61530ed0eecb5fc31a85)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I8a612dce000931835054086c1b02ebfc43dc57d2
Reviewed-on: http://review.coreboot.org/8718
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
With BOARD_VARIANT_AP148 configuration option enabled the image will
be built for 512MB DRAM instead of 1024MB and the
mainboard_part_number field in the lb_mainboard entry will be set to
"AP148" instead of "Storm".
BUG=chrome-os-partner:30440
TEST=manual
. built and booted both AP148 and proto0 all the way to reading the
kernel
. verified that the config file includes correct part number and
memory size
. verified proper machine IDs reportted when starting the kernel
Original-Change-Id: Ie609544a460fc991e66e8b95e8d7a3ed5e845f7b
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/207427
Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit a80ab00f27eef9e3aa2f761659d6945d6fce2ef6)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I477e672dc4f48fa9c9893bf0759704501ea07b1a
Reviewed-on: http://review.coreboot.org/8590
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
The actual storm device has a single USB interface, which needs to be
explicitly turned on using GPIO51.
BUG=chrome-os-partner:29871
TEST=verified that depthcharge finds and boots a kernel from USB stick
Original-Change-Id: Iaf868812c96e1e3289b9403855c4cc8f87c1e368
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/205329
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org>
(cherry picked from commit aa22376ffac22309a298dfa844e7f61c97d57d3e)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ic0f34622e61a65a0540c0f3fca26fb057fa85fb7
Reviewed-on: http://review.coreboot.org/8147
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
This patch adds code to initialize the two DWC3 USB host controllers and
their associated PHYs to the IPQ806x SoC (closely imitating the existing
DWC3 implementation for Exynos5), and uses them to initialize USB on the
Storm mainboard.
BUG=chrome-os-partner:29375
TEST=Hack up netboot to get around missing SPI flash, load a file over
TFTP. Hack a storage read into the storage attach function, dump the
data and confirm that it looks right. Enable USB debugging and confirm
3.0 devices get enumerated at SuperSpeed (mostly).
Original-Change-Id: Iaf7b96bef994081ca222b7de9d8e8c49751d3f1d
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/202157
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
(cherry picked from commit 6349e7281d5accb1247acb0537a48fa3a5e1bf97)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I749d265d45c6a807a7559bd4df2490a6eb8067af
Reviewed-on: http://review.coreboot.org/8056
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
