Commit graph

12 commits

Author SHA1 Message Date
Angel Pons
6bd99f9ada soc/intel/skylake: Clean up SD GPIO handling
This is to align with newer platforms.

Change-Id: If33ea3a7835ec071be3fd060f9712c47678bd6bf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50963
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01 19:37:36 +00:00
Elyes HAOUAS
5ba154a597 src: Use space after 'if', 'for'
Change-Id: I5d3a5ede47aefc7cc2ee330f8a0bcded16138764
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44173
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-05 11:37:00 +00:00
Patrick Georgi
6b5bc77c9b treewide: Remove "this file is part of" lines
Stefan thinks they don't add value.

Command used:
sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool)

The exceptions are for:
 - crossgcc (patch file)
 - gcov (imported from gcc)
 - elf.h (imported from GNU's libc)
 - nvramtool (more complicated header)

The removed lines are:
-       fmt.Fprintln(f, "/* This file is part of the coreboot project. */")
-# This file is part of a set of unofficial pre-commit hooks available
-/* This file is part of coreboot */
-# This file is part of msrtool.
-/* This file is part of msrtool. */
- * This file is part of ncurses, designed to be appended after curses.h.in
-/* This file is part of pgtblgen. */
- * This file is part of the coreboot project.
- /* This file is part of the coreboot project. */
-#  This file is part of the coreboot project.
-# This file is part of the coreboot project.
-## This file is part of the coreboot project.
--- This file is part of the coreboot project.
-/* This file is part of the coreboot project */
-/* This file is part of the coreboot project. */
-;## This file is part of the coreboot project.
-# This file is part of the coreboot project. It originated in the
- * This file is part of the coreinfo project.
-## This file is part of the coreinfo project.
- * This file is part of the depthcharge project.
-/* This file is part of the depthcharge project. */
-/* This file is part of the ectool project. */
- * This file is part of the GNU C Library.
- * This file is part of the libpayload project.
-## This file is part of the libpayload project.
-/* This file is part of the Linux kernel. */
-## This file is part of the superiotool project.
-/* This file is part of the superiotool project */
-/* This file is part of uio_usbdebug */

Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11 17:11:40 +00:00
Furquan Shaikh
3b54fdf282 soc/intel: Constify struct device *param to sd_fill_soc_gpio_info
sd_fill_soc_gpio_info() does not need to modify device
structure. Hence, this change makes the struct device * parameter to
this function as const.

Change-Id: I237ee9640ec64061aa9ed7c65ea21740c40b6ae2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-04-28 19:50:07 +00:00
Angel Pons
3bd1e3db9c soc/intel/skylake: Use SPDX for GPL-2.0-only files
Done with sed and God Lines. Only done for C-like code for now.

Change-Id: I7354edb15ca9cbe181739bc2a148f16bb85ab118
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2020-04-06 19:12:54 +00:00
Patrick Georgi
1c6d8a9cf4 soc: Remove copyright notices
They're listed in AUTHORS and often incorrect anyway, for example:
- What's a "Copyright $year-present"?
- Which incarnation of Google (Inc, LLC, ...) is the current
  copyright holder?
- People sometimes have their editor auto-add themselves to files even
  though they only deleted stuff
- Or they let the editor automatically update the copyright year,
  because why not?
- Who is the copyright holder "The coreboot project Authors"?
- Or "Generated Code"?

Sidestep all these issues by simply not putting these notices in
individual files, let's list all copyright holders in AUTHORS instead
and use the git history to deal with the rest.

Change-Id: I4c110f60b764c97fab2a29f6f04680196f156da5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2020-03-18 16:44:46 +00:00
Kyösti Mälkki
8950cfb66f soc/intel: Use config_of()
Change-Id: I0727a6b327410197cf32f598d1312737744386b3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: David Guckian
2019-07-18 15:25:35 +00:00
Jacob Garber
e1909eea5c soc/intel/skylake: Correct GPIO pointer assignment
We need to store the acpi_gpio struct, not save its address.

Found-by: Clang Static Analyzer
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I41c8bf10ce72bec736da97ccc33f9ada49804dc1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-05-16 10:02:42 +00:00
Bora Guvendik
a677feca88 soc/intel/skylake: Use SCS common code
This patch uses common SCS library to setup
sd card.

Change-Id: I06898e30a9b39f169b35f581a3ee09238f0f40c4
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/20217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-06-16 17:37:13 +02:00
Furquan Shaikh
5b9b593f2f acpi: Add ACPI_ prefix to IRQ enum and struct names
This is done to avoid any conflicts with same IRQ enums defined by other
drivers.

BUG=None
BRANCH=None
TEST=Compiles successfully

Change-Id: I539831d853286ca45f6c36c3812a6fa9602df24c
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18444
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-22 22:19:19 +01:00
Duncan Laurie
ffc9990ece acpi: Change device properties to work as a tree
There is a second ACPI _DSD document from the UEFI Forum that details
how _DSD style tables can be nested, creating a tree of similarly
formatted tables.  This document is linked from acpi_device.h.

In order to support this the device property interface needs to be
more flexible and build up a tree of properties to write all entries
at once instead of writing each entry as it is generated.

In the end this is a more flexible solution that can support drivers
that need child tables like the DA7219 codec, while only requiring
minor changes to the existing drivers that use the device property
interface.

This was tested on reef (apollolake) and chell (skylake) boards to
ensure that there was no change in the generated SSDT AML.

Change-Id: Ia22e3a5fd3982ffa7c324bee1a8d190d49f853dd
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15537
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-08 17:21:26 +02:00
Duncan Laurie
b25a45ca46 skylake: Add SD card device to configure card detect GPIO
Add a PCI driver for the skylake SD card device and have it generate
an entry in the SSDT for the card detect GPIO if it is provided by the
mainboard in devicetree.

This sets up a card detect GPIO configuration that will trigger an
interrupt on both edges with a 100ms debounce timeout and can wake the
SD controller from D3 state.

The GpioInt() entry is bound to the "cd-gpio" device property which will
be consumed by the kernel driver.

The resulting ACPI output in the SSDT will be combined with the SDXC
device declaration in the DSDT.

Example:

Scope (\_SB.PCI0.SDXC)
{
  Name (_CRS, ResourceTemplate () {
    GpioInt (Edge, ActiveBoth, SharedAndWake, PullNone, 10000,
             "\\_SB.PCI0.GPIO", 0, ResourceConsumer) { 35 }
  })
  Name (_DSD, Package () {
    ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
    Package () {
      Package () { "cd-gpio", Package () { \_SB.PCI0.SDXC, 0, 0, 1 } }
    }
  })
}

Change-Id: Ie4c1bfadd962cf55a987edb9ef86e92174205770
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/14995
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-31 18:46:39 +02:00