Commit Graph

14219 Commits

Author SHA1 Message Date
Patrick Georgi 091b4ae7de drivers/i2c/tpm: push tpm driver from verstage to libverstage
That way it's available wherever the verstage code ends up, bootblock,
verstage or romstage.

Change-Id: I0665e297f199acd60cff93e1b39812f183115d33
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10707
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30 08:19:36 +02:00
Patrick Georgi 5f2055d0d9 chromeos: push vbnv_* accessors from verstage to libverstage
That way they're available wherever the verstage code ends up, bootblock,
verstage or romstage.

Change-Id: I6e59a40761f95a98d96a9b72e3bbcc59caae9b1a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10706
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30 08:19:26 +02:00
Patrick Georgi f73f06cb73 google/cosmos: romstage needs the accessor functions for buttons
In Chrome OS mode, the romstage tries to interpret the various buttons on the
device, so it needs access to the accessor functions.

Change-Id: Iecfd37e79883d826e15c474d77095fbbbb2b7cea
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10705
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30 08:18:46 +02:00
Patrick Georgi dea4bb676a google/storm: romstage needs the accessor functions for buttons
In Chrome OS mode, the romstage tries to interpret the various buttons on the
device, so it needs access to the accessor functions.

Change-Id: I59a4f892ca84d475d8f46c8f8c1906dae10ad32d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10704
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30 08:18:38 +02:00
Patrick Georgi 3cbbf19075 qualcomm/ipq806x: Fix uart in verstage
An old Kconfig symbol from Chrome OS survived into the Makefile (but is
nowhere declared or used). Use the same symbol as for uart.c in the other
stages.

Change-Id: I7a6f1b82254e888d6f2d65d6cff87c4d546ec097
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10703
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-06-30 08:18:22 +02:00
Patrick Georgi 954781f4f8 qualcomm/ipq806x: centralize vboot configuration
vboot configuration (separate stage or not, which stage loads romstage)
depends on SoC properties (eg. amount of SRAM), not on board specifics, so
move this part of the configuration to the SoC.

Change-Id: I70b4cd1794ddf2aba7cdae94859ea1d76ae019f4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10702
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30 08:18:12 +02:00
Patrick Georgi f0a97bf75e google/veyron: Fix building with CHROMEOS enabled
romstage requires some button accessor functions for the Chrome OS boot flow.

Change-Id: I3f90d66b103e0610931c183dd5f5679ca6f910f6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10697
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-06-30 08:17:52 +02:00
Patrick Georgi 2268b3b750 arch/arm64: Avoid race condition when building bl31
The arm-trusted-firmware build system may not create the final bl31.elf file
atomically, confusing our make to try to use it before it's ready.
Hence insert a (hopefully, but not guaranteed to be atomic) file move.

Change-Id: Iffc80467e0f4bbc96fc62414d4abfaa7b42634f4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10700
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-06-30 08:11:39 +02:00
Julius Werner da0098a4d0 mainboard: Add Veyron_Shark
This patch adds the Veyron_Shark mainboard as a clean copy of Veyron_Speedy.

- board-ID differentiation removed, see mainboard.c
- speedy -> shark rename

BRANCH=None
BUG=None
TEST=Compiled.

Change-Id: I3b743a97f152f49647eee87be8f1497377ccacb4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ac2ca328adf7e0dd879f51bbeae3cc11bceebf86
Original-Change-Id: I8a7cc9acb199ecf23b388c66f6885931ea3ec219
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/276490
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/10699
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-06-30 08:11:26 +02:00
Duncan Laurie a51815119f hardwaremain: Move init_timer() call to before console init
The 8250 MMIO uart driver calls udelay, and if that is the first
call then it will also call printk in init_timer() which can result
in a deadlock trying to acquire the console lock.

There are a few options to prevent this:
1) remove the printk in init_timer which removes a useful debug message
2) change the udelay() to cpu_relax() in uart8250mem.c
3- move the init_timer() call in ramstage main() to be called earlier

Since hardwaremain.c:main() already has an explicit call to init_timer()
on x86 it is an easy change to move this to happen before the console
is initialized.

BUG=chrome-os-partner:40857
BRANCH=none
TEST=boot on glados with serial output through ramstage

Change-Id: I8a8d8cccdd0b53de9de44600076bfad75e4f5514
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 744610f72628a944582925933b286f65bde630d9
Original-Change-Id: Ic1fdafaea5541c6d7b1bb6f15399c759f484aa74
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/275157
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10698
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-06-30 08:11:16 +02:00
Patrick Georgi fbc45a60eb arch/arm64: Fix compilation without CONFIG_SMP
Compilers aren't happy with a declaration of boot_cpu() after defining
boot_cpu to 1.

Change-Id: I22d0db61646f3e226e5996fa94223ffbb6b760e5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10696
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30 08:11:03 +02:00
Stephen Barber e72487944f t210: Set UTMIP_PCOUNT_UPDN_DIV to 0
Improve USB device mode stability as per suggestion by Laurent.

BUG=chrome-os-partner:40929
BRANCH=smaug
TEST=flash firmware and check that USB device mode is still functional.

Change-Id: Id6dd7bb2e1632c512cfdf7d38a16de26a8f71471
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4298741ef4440c8bd8dac4a9f9eaa55ba560cbfb
Original-Change-Id: I07d6c46d215f2ccf2c76c580f59c4fa0d519eaa5
Original-Signed-off-by: Stephen Barber <smbarber@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/278030
Original-Reviewed-by: Benson Leung <bleung@chromium.org>
Original-Tested-by: Benson Leung <bleung@chromium.org>
Reviewed-on: http://review.coreboot.org/10695
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30 08:10:54 +02:00
Furquan Shaikh 67246f4738 arm64: Fix Kconfig issues for secure OS loading
BUG=chrome-os-partner:40713
BRANCH=None
TEST=Compiles successfully with and without SECURE_OS config selected

Change-Id: I93e9726712a1992f1788d60891d5f6917bba3767
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 535ac9ffd1199b047734da0a9ee257d468b3fbb1
Original-Change-Id: Ic70a0b57816a5f3af548edafd82ba3783825a174
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/274416
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/10694
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30 08:10:46 +02:00
Furquan Shaikh a384c2899d arm64: Add support for loading secure os
Add support for loading secure os and pass its entrypoint as bl32 params
to bl31 stage.

BUG=chrome-os-partner:40713
BRANCH=None
TEST=Compiles successfully and loads secure os

Change-Id: I1409ccb7344c1d1b1ddc2b321fdae1beea2f823d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d3dc19025ff11c1e0590306230df7654ef9ad086
Original-Change-Id: Iafd540bf2906d10b5ee009e96179121fecbf5e11
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/273719
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/10693
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30 08:10:28 +02:00
Patrick Georgi add740ac28 Add Kconfig flag to specify if there's a lid switch
Not all devices have a lid switch, so we need to state this
somehow. Since the alternative would be to extend get_lid_switch()'s
semantics to become a tri-state (open, closed, N/A), do this
through Kconfig.

BRANCH=none
BUG=chromium:446945
TEST=none

Change-Id: Icc50f72535f256051a59925a178fb27b2e8f7e55
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d20a1d1a22d64546a5d8761b18ab29732ec0b848
Original-Change-Id: Ie8ac401fbaad5b5a9f1dec2b67847c81f4cc94aa
Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/273850
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Queue: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10692
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30 08:10:19 +02:00
Patrick Georgi 08b8785aeb Expose get_lid_switch() in romstage
The function was used locally and in ramstage to set some
coreboot tables. It's also needed in romstage to deal with
"lid closed" behaviour.

BRANCH=none
BUG=chromium:446945
TEST=none

Change-Id: I8ad7061328c45803699321aa9f5edb0ed2288a8d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 78281a104fb9d79696a6ceb2a9a89a391146a424
Original-Change-Id: I56314b9dc9062dd61671982e7ec0ff15d7eb1bae
Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/273609
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Queue: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10691
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30 08:10:11 +02:00
Furquan Shaikh f7a5b56297 cbfstool: Handle elf with different virtual and physical address
Adds support in cbfstool to adjust the entry field based on the
virtual and physical address in program header.

BUG=chrome-os-partner:40713
BRANCH=None
TEST=Verified correct entry point address. Trusty loads and boots correctly.

Change-Id: I215b0bea689626deec65e15fb3280e369d816406
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 32a740f0b628c124d3251cc416e2fc133bb15c57
Original-Change-Id: Ia999b5c55887c86ef1e43794ceaef2d867957f4d
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/274087
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/10690
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30 08:09:58 +02:00
huang lin 41e2499734 libpayload: add UDC driver for Designware controller
Found in rockchips rk3288 as used in google/veyron.

BUG=None
TEST=None
BRANCH=None

Change-Id: I2f2c36c5bea3986a8a37f84c75608b838a8782ae
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 59a0bcd97e8d0f5ce5ac1301910e11b01e2d24b1
Original-Change-Id: Ic89ed54c48d6f9ce125a93caf96471abc6e8cd9d
Original-Signed-off-by: Yunzhi Li <lyz@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/272108
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Lin Huang <hl@rock-chips.com>
Original-Tested-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: http://review.coreboot.org/10689
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30 08:09:49 +02:00
Furquan Shaikh 066cc85e22 EC: Add new EC host event for FASTBOOT_MODE request
BUG=None
BRANCH=None
TEST=Compiles successfully

Change-Id: Id24b87e03097eb93c0b4316c853575629e5502aa
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cf80de709d2bf310a3a37b9897063d2d833933b9
Original-Change-Id: Ia5d42efd81b59c1b99d3be5be6d0c770ad602429
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/280879
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/10688
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30 08:09:41 +02:00
Furquan Shaikh a4b718cc2d UDC: Correct cleaning out memory for string descriptors
BUG=chrome-os-partner:41687
BRANCH=None
TEST=Compiles successfully and fastboot devices reports correct serial
number even after re-connection.

Change-Id: I4741a5d6333523eb47c27b4a20c4ef3f1e853d76
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6249b1e35391550d788f56a7b3e7a49ae19f0c93
Original-Change-Id: I1348c33f354d11e3c29ccd9da9948cfbeb60aa9e
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/281192
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/10687
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30 08:09:31 +02:00
Furquan Shaikh ed1a4bbb60 udc/chipidea: Allow force_shutdown of connection
Allow force shutdown operation of the connection in case where the
cable is disconnected and reconnected back.

BUG=chrome-os-partner:41687
BRANCH=None
TEST=Compiles successfully and fastboot works fine even with
reconnection of cable

Change-Id: I8eb1217b4a9ad6ce8a2a40db329eca1930eda089
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3d7ab65c459caa4ec526b99a1aee1a31e9cb80da
Original-Change-Id: I354c44e0ed2211cb2c4c1ae653d201b7d15ea932
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/281066
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/10686
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30 08:09:22 +02:00
David Hendricks 14610ec20a veyron_danger: Update SDMMC power on/off code for v2
This re-factors SDMMC power on/off to make corrections and take
differences between board versions into account. To avoid similar-
but-different case switch statements in romstage.c and mainboard.c,
power on/off functions for SDMMC are split into their own .c file.

BUG=none
BRANCH=none
TEST=built and booted of micro-SD card on Danger v2

Change-Id: Ib3069c35ceff1ff98b49579a6298681c1390beee
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: eecfee4a5dd39073b5f966a25991a594b3c4b519
Original-Change-Id: Id86ae7f40687e843ffc4e7769309d4678ad54f49
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/280853
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/10685
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30 08:09:13 +02:00
David Hendricks 4039822dc4 veyron_danger: Add basic HDMI support
This adds a configure_hdmi() function that drives the HDMI
enable output high and configures the iomux.

We'll add EDP/HDMI auto-detection in an upcoming patch.

BUG=none
BRANCH=none
TEST=set vop_mode to 1 in Danger's devicetree.cb and saw
dev mode screen output to HDMI display.

Change-Id: I2a208059fee74d436b5a5bedbc677bc59525f935
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 721f326319f727afcf73a0c21d20d26cb463ad71
Original-Change-Id: I139d39749963d4121aaeec0c3da37d825ffa94ac
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/280849
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/10684
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30 08:09:02 +02:00
Stefan Reinauer 9bca4ba078 vboot2: Enable VBOOT_DYNAMIC_WORK_BUFFER on x86
Change-Id: Iaadbd52d948000d1ed46865b83bdb0f4926ca429
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10677
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-29 23:20:05 +02:00
Patrick Georgi aabfe05bff vboot2: consolidate vboot2 buffer initialization
Instead of calling the init function to clear out vboot2 data structures in
multiple places, move the function and call close to verstage_main().

Change-Id: If42e18a8e4581f22f7a7aced70ccbe3188bb0cd5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10701
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-06-29 23:13:17 +02:00
Jonathan A. Kollasch 619781493a mainboard/msi/ms7135: DSDT: fix PCI and AGR interrupts
Tested with interrupting AGP card in AGR slot.
PCI slots tested with 3-function OHCI/EHCI USB 2.0 card,
covering the INTA-INTC lines in each.

Change-Id: I0f8aeba90890a76a7cf9cbee9be7bcf919d1e39a
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/10644
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-29 18:28:59 +02:00
Jonathan A. Kollasch 7a75aff3ff mainboard/msi/ms7135: only #include necessary headers in acpi_tables.c
Change-Id: I0837a2d1e0d8e233f6ef7d7212ce76f2223d19b9
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/10641
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-29 18:19:10 +02:00
Patrick Rudolph 4275ff86fa intel raminit: check correct registers in channel_test
Found while doing code review. No actual problem was observed.

Test system:
* Intel IvyBridge
* Gigabyte GA-B75M-D3H

Verify byte-lane error count registers 0 to 7 instead of verifying byte-lane
error count register 0 eight times in a row.

Change-Id: Ife6ac6558b2f65ad947870cde5f15d90560ce6d9
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: http://review.coreboot.org/10664
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-28 22:42:11 +02:00
Patrick Rudolph 3247916d11 intel raminit: properly handle DDR3 DIMMs with address mirroring
Issue observed:
DDR3 DIMM with address mirroring enabled doesn't work when placed in
slot 1 and slot 0 is empty. It does work when placed in slot 0 and
slot 1 is empty.

Test system:
* Intel IvyBridge
* Gigabyte GA-B75M-D3H
* Kingston KVR1066D3N7/4G (address mirroring enabled DIMM)

Problem description:
The address mirror enable bit is slot-swapped in the DIMM mapping code,
but none of the remaining code is aware of DIMM mapping. Removing the
code, that is swapping the mirror enable bit, results in the correct
behaviour. The DIMM is now working in every slot.

Change-Id: I7a51bbc8d156209449fd67c954930835814a40ee
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: http://review.coreboot.org/10652
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-28 22:40:41 +02:00
Timothy Pearson 039edebc08 mainboard/asus/kfsn4-dre: Enable VGA support
The ASUS KFSN4-DRE has full native VGA support, enable support for the
VGA device by default in the Kconfig file.

Change-Id: I09fc8845a30f26ca49f3547812f9784621ff4b5e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/10673
Tested-by: build bot (Jenkins)
Reviewed-by: Francis Rowe <info@gluglug.org.uk>
Reviewed-by: Martin Roth <gaumless@gmail.com>
2015-06-27 05:59:16 +02:00
Martin Roth b6c2f8919e lenovo/g505s: Add System Board ID to fix ACPI warning
Add the System Board Hardware ID to fix the warning:

dsdt.aml     88:  Device (MB) {
Warning  3141 -           ^ Missing dependency
(Device object requires a _HID or _ADR in same scope)

Change-Id: Ie97b1e6792c8d4c8db2500cef6a79881b7ff94c8
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10669
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-27 02:48:42 +02:00
Martin Roth 9a4cbc9d15 google/parrot: Add System Board ID to fix ACPI warning
Add the System Board Hardware ID to fix the warning:

dsdt.aml     88:  Device (MB) {
Warning  3141 -           ^ Missing dependency
(Device object requires a _HID or _ADR in same scope)

Change-Id: I063580142ae8053fdc05e165c01e86b8b7cd5ca6
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10668
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-27 02:48:11 +02:00
Martin Roth 0458370bf7 Kconfig: Remove unnecessary and incorrect MRC_CACHE symbols
Because of a misunderstanding of how Kconfig files are parsed, the
OVERRIDE_MRC_CACHE_LOC symbol was added to make sure that the value
was correctly set.  This is not needed unless for some reason the
Kconfig parser is suddenly rewritten to parse everything differently.

At some point, the value in the FSP's Kconfig file was updated to
OVERRIDE_CACHE_CACHE_LOC, while the entries in the mainboard
Kconfig files were not updated.  This resulted in the default values
not getting set correctly by default on the FSP Bay Trail boards.

This removes the whole bunch of incorrect and unnecessary symbols and
just sets the default for the MRC cache location directly.

Change-Id: I1cec758576866b7e0677272b8309bfde8d4a1ee4
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10611
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-27 02:47:39 +02:00
Stefan Reinauer 302a2ec7d1 amd/inagua: broadcom driver 64bit fix
Change-Id: I357f11fa74bac5f9e1ecfc91a91f06127334752d
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10596
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-27 01:01:26 +02:00
Patrick Georgi bfa51979dc rockchip/rk3288: complete vboot configuration and move to SoC
Where vboot verification can start, and how the code flow looks like is more a
property of the SoC (and its properties, like amount of SRAM) rather than the
board.

Change-Id: I610153ea4ceddc226d8cc3e17a515e41fc0479cf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10662
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-26 23:30:39 +02:00
Patrick Georgi 463d665cb1 google/chromeos: always enable VBOOT_VERIFY_FIRMWARE with CHROMEOS
Change-Id: Icc3cf64f259d4ebd7900ad91163276774e5422ab
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10661
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-26 23:30:13 +02:00
Patrick Georgi 0d5f27b8bb vboot: Init vb2 work memory area before calling verstage
Otherwise it'll determine some offsets from uninitialized data and hilarity
ensues.

Change-Id: I6a671987857cfd3f3cd6078aebd13dd09fc79020
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10660
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-26 23:30:01 +02:00
Patrick Georgi 1dc22f5cbc google/veyron_speedy: Add chromeos.c to romstage
vboot requires it.

Change-Id: Iae2310c9b9c311c3f64b8417295685261ba404b0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10659
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-26 23:29:51 +02:00
Stefan Reinauer 987493300d x86: Move architecture selection from linker script to Makefile.inc
Change-Id: I5efd3cb3e6970b5740f740507244a1ab823e0bb6
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10590
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-26 22:44:10 +02:00
Stefan Reinauer eec2db4da7 prog_loader: Play nice with gc-sections
With an x86_64-elf toolchain, this code that is unused
outside of ramstage, is causing undefined references.

Help the compiler along a little bit by conditionally compiling
the code in ramstage only.

Change-Id: I75518149b53c24eda4b985b0fef856447e196dec
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10585
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-26 22:43:46 +02:00
Lee Leahy 3e5bc1feab soc/intel/common: Restrict common romstage/ramstage code to FSP
Restrict the use of the common romstage/ramstage code to FSP 1.1

BRANCH=none
BUG=None
TEST=Build and run on cyan/sklrvp

Change-Id: Ifbdb6b4c201560a97617e83d69bf9974f9411994
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10653
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-06-26 00:01:57 +02:00
Lee Leahy fbe276b96f Braswell: Remove copyright address
Remove the copyright address from all of the files.

BRANCH=none
BUG=None
TEST=None

Change-Id: I7190e34e165e5652d33902440fa08253b77f4af2
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10337
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-06-25 21:51:17 +02:00
Lee Leahy 32471729d9 Braswell: Add Braswell SOC support
Add the files to support the Braswell SOC.

BRANCH=none
BUG=None
TEST=Build for a Braswell platform

Change-Id: I968da68733e57647d0a08e4040ff0378b4d59004
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10051
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-06-25 21:50:48 +02:00
Martin Roth 5fe62efb77 soc/intel/common/Kconfig: Fix warning & whitespace
Because of a missing close quote, we have the warning:
src/soc/intel/common/Kconfig:52:warning:multi-line strings not supported

This was added in commit 0946ec37 -Intel Common SOC:Add romstage support

The whitespace issue - using spaces instead of a leading tab was added
in the same commit.

Change-Id: I429c66afb5a7e10ca0e0ef619ac46722c63fb376
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10654
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2015-06-25 20:25:30 +02:00
zbao 3ad1f1ca5f amd/pi/hudson: Fill ROMSIG with 0xFF instead of 0
Besides the first five DWORDs, the offsets 0x40 & 0x41
are used to save SPI settings. They should only be 0xFF
for being written.

Other parts in ROMSIG are also changed to 0xFF for potential
requirement.

Change-Id: I61ea8295d5ee8ffbbd0cfcf9e4bece770d70e1f2
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/10651
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-25 04:06:59 +02:00
Martin Roth 128043edee Intel FSP 1.1: Move Kconfig comment inside 'if' block
- Move the 'Intel FSP' Kconfig comment inside the 'if' block so that it
doesn't show up on platforms that aren't using it.
- Update the comment to reflect that this is version 1.1 of the FSP
interface.

Change-Id: I7182c5b07332c4f95620f7374526ab1de0484d01
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10650
Tested-by: build bot (Jenkins)
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2015-06-25 00:02:37 +02:00
Lee Leahy 40c0543108 Intel/common: Remove copyright address
Remove the copyright address from the remaining files.

BRANCH=none
BUG=None
TEST=None

Change-Id: I026a0ff2bcb6c9580b45700edab446b787223007
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10336
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-06-24 17:05:35 +02:00
Lee Leahy 0946ec37aa Intel Common SOC: Add romstage support
Provide a common romstage implementation for the Intel SOCs.

BRANCH=none
BUG=None
TEST=Build for Braswell

Change-Id: I80f5f8f0f36e9023117b07d4af5c806fff8157b6
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10050
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-06-24 17:05:06 +02:00
Lee Leahy 4a8c19cc90 FSP 1.1: Bring source up-to-date
Use 3rdparty/blobs subdirectory for binary files
Display the MTRRs after TempRamExit and before the MTRR setup
Clear all of the variable MTRRs before the MTRR setup
Define the FSP attributes location and bits
Properly display the FSP_RESERVED_MEMORY_RESOURCE_HOB and the
FSP_BOOTLOADER_TOLUM_HOB.

BRANCH=none
BUG=None
TEST=Build and run on cyan

Change-Id: I788a5f1e7676b1a06c1bcd66ddbd0a2249cad47c
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10589
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-24 17:03:49 +02:00
Lee Leahy bfdf2489f0 cpu/x86: Add more MTRR symbols
BRANCH=none
BUG=None
TEST=Build and run on strago

Change-Id: Ia3740353eb16f2a2192cad8c45645f845bf39475
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10588
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-24 17:03:29 +02:00