GNUBoot/coreboot-kgpe-d16
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9 commits

Author SHA1 Message Date
Xavi Drudis Ferran
e660f04161 Fix warnings (that become errors) in AMDHT for certain configurations (unused functions) 
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5704 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2010-08-17 06:12:59 +00:00
Zheng Bao
23ffe8b690 The number of cores is got by reading the bit 15,13,12 of [0,24,3,e8]. 
The bit 15 seems to be a new feature when CPU started to have more than 4
cores.

Zheng

Yes, this was add for revD.

Marc Jones

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5684 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2010-08-05 06:12:16 +00:00
Stefan Reinauer
306343266b zero warnings days. 
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5394 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2010-04-09 13:35:03 +00:00
Stefan Reinauer
26afd18e10 remove more warnings. 
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5350 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2010-04-02 22:31:35 +00:00
Stefan Reinauer
8b547b1980 reduce warnings in MCP55 and Fam10 code 
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5325 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2010-03-30 09:56:35 +00:00
Marc Jones
212486e9f6 Clean up AMD FAM10 HT variable initialization. The structure init is cleaner, avoid compiler warnings, and matches the AMD example code more closely. 
Signed-off-by: Marc Jones <marc.jones@amd.com>

Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3425 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2008-07-17 19:50:37 +00:00
Marc Jones
aee0796506 Clean up comments, whitespace, and copyright date in the AMD HT code. 
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Marc Jones <marc.jones@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3423 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2008-07-16 21:09:31 +00:00
Stefan Reinauer
7e61e45402 Please bear with me - another rename checkin. This qualifies as trivial, no 
code is changed.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3052 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2008-01-18 10:35:56 +00:00
Marc Jones
8ae8c88220 Initial AMD Barcelona support for rev Bx. 
These are the core files for HyperTransport, DDR2 Memory, and multi-core initialization.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Reviewed-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Myles Watson <myles@pel.cs.byu.edu>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3014 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2007-12-19 01:32:08 +00:00