This will be common for all boards, so move it to the chipset device
tree.
TEST=CPU cluster and LAPIC still show up in console logs.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia49e7b4cfc09c60b6152b8ccc47f37b6adc1e319
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50613
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We now pass the ACPI SCI IRQ to the OS, so make sure the board routes it
correctly.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I1b4d5e0bfb1d9df9ac8a8c41cdf466a67f2673d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
I left most everything as NC since we don't expose the values to the
OS yet.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7c3195ef27091f1bc61892c475ffe09137b63083
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50511
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change enables vboot support. To use it add CHROMEOS=y to your
config.
TEST=Boot majolica and see verstage run, and then see depthcharge load.
coreboot-4.13-1730-g881092709a5e Fri Feb 5 23:50:28 UTC 2021 verstage starting (log level: 8)...
Phase 1
FMAP: area GBB found @ 805000 (458752 bytes)
VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0
Phase 2
Phase 3
FMAP: area GBB found @ 805000 (458752 bytes)
FMAP: area VBLOCK_A found @ 30000 (8192 bytes)
FMAP: area VBLOCK_A found @ 30000 (8192 bytes)
VB2:vb2_verify_keyblock() Checking keyblock signature...
VB2:vb2_verify_digest() HW RSA forbidden, using SW
VB2:vb2_rsa_verify_digest() HW modexp forbidden, using SW
FMAP: area VBLOCK_A found @ 30000 (8192 bytes)
FMAP: area VBLOCK_A found @ 30000 (8192 bytes)
VB2:vb2_verify_fw_preamble() Verifying preamble.
VB2:vb2_verify_digest() HW RSA forbidden, using SW
VB2:vb2_rsa_verify_digest() HW modexp forbidden, using SW
Phase 4
FMAP: area FW_MAIN_A found @ 32000 (3137280 bytes)
VB2:vb2api_init_hash() HW crypto forbidden by TPM flag, using SW
VB2:vb2_verify_digest() HW RSA forbidden, using SW
VB2:vb2_rsa_verify_digest() HW modexp forbidden, using SW
Saving secdata firmware
Saving secdata kernel
Saving nvdata
Slot A is selected
FMAP: area FW_MAIN_A found @ 32000 (3137280 bytes)
CBFS: mcache @0x02017000 built for 9 files, used 0x1ec of 0x800 bytes
CBFS: Found 'fallback/romstage' @0x0 size 0x753c in mcache @0x02017000
BS: verstage times (exec / console): total (unknown) / 116 ms
coreboot-4.13-1730-g881092709a5e Fri Feb 5 23:50:28 UTC 2021 romstage starting (log level: 8)...
Family_Model: 00a50f00
FMAP: area FW_MAIN_A found @ 32000 (3137280 bytes)
CBFS: Found 'fspm.bin' @0x15440 size 0x2257d in mcache @0x02017138
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I43f0c6e33649332057f41f8813a86571b06032f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
They all operate on that file, so just add it globally.
Change-Id: I953975a4078d0f4a5ec0b6248f0dcedada69afb2
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Target added to INTERMEDIATE all operate on coreboot.pre, each modifying
the file in some way. When running them in parallel, coreboot.pre can be
read from and written to in parallel which can corrupt the result.
Add a function to create those rules that also adds existing
INTERMEDIATE targets to enforce an order (as established by evaluation
order of Makefile.inc files).
While at it, also add the addition to the PHONY target so we don't
forget it.
BUG=chromium:1154313, b:174585424
TEST=Built a configuration with SeaBIOS + SeaBIOS config files (ps2
timeout and sercon) and saw that they were executed.
Change-Id: Ia5803806e6c33083dfe5dec8904a65c46436e756
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49358
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Without the EC blob being present in the SPI flash, the board won't even
power up.
Change-Id: Ia3c50e86414bbc707bc33e28c636196c1be2f1e6
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This is an adapted copy of mainboard/example/min86 that is currently
only used for Jenkins to test the SoC code in soc/amd/cezanne and isn't
expected to reach boot block at the moment. It will be extended in
future follow-up commits.
Change-Id: I6806955952fbfa3227294cfc44fdf9156140e933
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
