Commit Graph

10614 Commits

Author SHA1 Message Date
Kyösti Mälkki 931c1dcec0 stdlib: Drop duplicates of min() and max()
Change-Id: Ib2f6fad735e085d237a0d46e0586e123eef6e0e2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6161
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-01 10:15:26 +02:00
Kyösti Mälkki f41cb4ecd2 ROMCC: Fix collision with token name max
Even with !defined(__ROMCC__) in the file, romcc chokes on these
parameter names after we declare common max() macro in stdlib.h.

Change-Id: Id4f2aa61d9c5b19f428452cd475b1b2ed9a70f52
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6165
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-01 10:14:46 +02:00
Edward O'Callaghan 42b716f119 northbridge/intel/nehalem/raminit.c: Extraneous parenthese
Equality comparison with extraneous parenthese, spotted by Clang.

Change-Id: I8d532392a0365753583ed441958e06d5da784587
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6124
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-30 18:20:20 +02:00
Edward O'Callaghan df3629b63c northbridge/amd/{gx2,lx}: Qualify pointer with `volatile`
There is no guarantee reading a dereferenced null pointer will not be
optimised away. Qualify the integer storage type with volatile. Clang
enforces this explicitness.

Change-Id: I31524141d70632cade0490c820936a3a8b570346
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6148
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-30 18:14:31 +02:00
Kyösti Mälkki 38a8fb0c18 x86 MTRR: Drop unused return value
It was never well-defined what value this function should return.

Change-Id: If84aff86e0b556591d7ad557842910a2dfcd3b46
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6166
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-30 17:55:36 +02:00
Kyösti Mälkki 599cda8228 Use MTRR defines
Change-Id: I60ae6dcb8c3b280fe74f27f4d61de70cc1ba190b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6123
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-30 17:55:16 +02:00
Edward O'Callaghan 2c342f5080 Makefile.inc: Detect if a working clang binary exists before set
Let us not assume the 'clang' binary exists and is working just because
the user selected it in .config

Change-Id: Iad3cbf4a7cda0e1c4d435fbe426b7247233973ea
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6141
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-06-30 06:31:27 +02:00
Edward O'Callaghan 480790b593 Makefile: HOSTCC set too late in clang builds
Currently we set HOSTCC=clang a little late meaning some minor bits
(utils/kconfig) are built with GCC. Move the assignment up the Makefile.

Change-Id: Ic72ad808eba0c0bf508bde34fb9bf0390c0b1d4d
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6140
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-06-29 19:17:49 +02:00
Edward O'Callaghan d2a7523cb1 northbridge/amd/gx2/raminit.c Halt func needs noreturn attrib
Missing "__attribute__((noreturn))" on halt function. This sync's the
implementation to be the same as that of amd/lx thereby avoiding
compiler warnings.

Change-Id: Iead16125805eb36ff875fba767cf8d4e5aa86715
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6157
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-29 15:04:48 +02:00
Edward O'Callaghan ec79d7a66e drivers/pc80/mc146818rtc_early.c: Silence unused func complaints
Clang complains these functions are unused since they find their way
into the bootblock of ROMCC boards by #including the .c file. These
static inlines should probably be moved into a header in reality.

Change-Id: I9d82a6befb0ac99afab6265f9d3649e419f2887d
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6122
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-06-29 15:03:49 +02:00
Edward O'Callaghan 78d33b649e southbridge/intel/ibexpeak/me.c: Silence warns about unused func
Move some __SMM__ functions under the #if preprocessor condition to
avoid warnings about unused functions.

Change-Id: I7f6fbc6a577032bc4e4635d91e8e94aecb517bd3
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6127
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-29 15:01:58 +02:00
Edward O'Callaghan caac5ef86d northbridge/amd: Remove some extraneous parentheses from if-statements
Spotted by Clang.

Change-Id: I38832da7b93d4ee18b8de3e80dc39513a8910221
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6149
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-29 13:05:25 +02:00
Edward O'Callaghan 4d7539eefd cpu/x86/pae/pgtbl.c: Unsigned comparison < 0 always false
Comparison of unsigned expression < 0 is always false.

Change-Id: Idf4e7846b50f4376a5d33515681efbd773d1caca
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6146
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-29 13:02:13 +02:00
Kyösti Mälkki 2f9b3afc84 AMD boards: Fix comment style and typos
Change-Id: Id630cc46b79a39e1786d42adbc21f3b9c3a051aa
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6118
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-29 09:40:35 +02:00
Patrick Georgi 25b56c3af5 build: remove -ccopts mechanism
We now use the slightly more familiar CFLAGS_* and CPPFLAGS_*
for the same purpose.

Change-Id: Ifd2bd13f67f71fa0a15611a6d11a6a4c7994271b
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5875
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-06-29 09:22:13 +02:00
Edward O'Callaghan d638c2b34b include/pc80/mc146818rtc.h: Inconsequential, comment ifdef maze
Change-Id: Ie1ec8dbcdbbe0f2b05fdb10b1dca43cfee2a58cb
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6120
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-29 09:05:37 +02:00
Edward O'Callaghan 95b0c3d75a arch/x86/include/bootblock_common.h: Sanitize header inclusion
Sanitize the inclusion of mc146818rtc.h in bootblock_common.h

Change-Id: I37d9ffd1375aedbf1f3eaa4ddce27e16166ce0b9
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6119
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-06-29 09:05:27 +02:00
Edward O'Callaghan 44fd0a0031 utils/cbfstool: No need to pass -g flag twice
Spotted by building with Clang.

Change-Id: I7ab97278d8bd586a71e453c8cc9d26dd6938c8d2
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6139
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-06-29 04:16:49 +02:00
Edward O'Callaghan efe2435fec cpu/amd/geode_gx2/cache_as_ram.inc: Remove illegal ASCII art
Embedding comments inside comments is illegal in the C specification,
Clang enforces this.

Change-Id: I0a468e4196034b00dfc5860fdbbab7788e4fef77
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6154
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-06-29 04:10:15 +02:00
Patrick Georgi 9c41063713 Don't add .eh_frame sections to SMM image
We don't need exception handlers and they waste space.

Change-Id: I98a34d1c9638e8c4168edbfb4b1cddde8a64623f
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/6105
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-28 16:40:50 +02:00
Patrick Georgi 91d6fc8118 armv7: We don't use CPPFLAGS anymore
CPPFLAGS is only used as qualified variant
(like CPPFLAGS_armv7) now.

Change-Id: If8b570ace4ac92d1fdb38ca3f7fef6c79d513a95
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5874
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2014-06-28 16:40:29 +02:00
Edward O'Callaghan b0195a3325 build: Pass correct disassembly flags in Clang build
On SVR4-derived platforms, the character `/' is treated as a comment
character, which means that it cannot be used in expressions. The
`--divide' option turns `/' into a normal character. This seems to be
needed with our local build of binutils since we don't yet use the
internal assembler/disassembler of the Clang tooling.

Change-Id: I344fc8670fd5d994f3b63308a513dd367aefc7f9
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5813
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-27 17:12:27 +02:00
Edward O'Callaghan 9b229858b2 lib/Makefile.inc: Stop gcc.c getting into SMM clang builds
The libgcc runtime workarounds found in gcc.c are not needed for
compiler-rt used by the Clang toolchain. Stop gcc.c from sneaking into
Clang builds while processing boards that use SMM code.

Change-Id: I51e8d517784721d28b4d951bd0bebc8b52682a8e
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6121
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-06-27 17:11:19 +02:00
Edward O'Callaghan 0ae068efdb src/console/post.c: Sanitize headers from preprocessor abuse
Continuing on from the rational given in:

a173a62 Remove guarding #includes by CONFIG_FOO combinations

Change-Id: I524713b21684f6fa99355614a1ab38aee9975790
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6091
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-06-27 04:23:40 +02:00
Edward O'Callaghan 5e19650686 include/device/device.h: Header is ROMCC tentative
This header is incompatible with ROMCC and its inclusion leads to 'odd'
build failures.

Change-Id: If31d774385796dcafe2fd48151e424b4c872aec3
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6103
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-06-27 04:22:26 +02:00
Kyösti Mälkki faaa253660 amd/persimmon jetway/nf81-t56n-lf: Fix whitespace and alignment
Change-Id: I76f017b0919e301eeb84e73eff21170bbc921ae2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6113
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-26 20:35:26 +02:00
Kyösti Mälkki 26c6543c35 AMD boards: Fix typos
Change-Id: I5df80e6445f390060372be8760c9b5e960e4a6e5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6117
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-26 20:33:28 +02:00
Kyösti Mälkki 8f87c3f397 AMD boards: Fix typos
Change-Id: If1dc4fd2204a2e4b6f84c75f385b8ff958d2251d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6112
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-26 20:31:55 +02:00
Kyösti Mälkki efa8a9dc21 AMD boards: Fix typos
Change-Id: I22180c3c2987396717864f04c59560029d088d53
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6111
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-26 20:31:19 +02:00
Kyösti Mälkki d874757a4f AMD boards: Fix typos
Change-Id: I92f3877b58d9acaa9578337e66107e9cd9f46043
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6110
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-26 20:30:03 +02:00
Kyösti Mälkki 6533b83c82 AMD boards: Fix typos
Change-Id: I090e98fbf28595d3917ef84e19bd6d6742f11b94
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6108
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-26 20:29:31 +02:00
Kyösti Mälkki 9533d836d7 PIRQ tables: Fix typos
Change-Id: I4d8abe3841378e06515e1b3a8f22d78425d08449
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6109
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-26 20:28:18 +02:00
Martin Roth 0b4b230163 bayleybay_fsp: Switch from EHCI controller to XHCI
- Disable the EHCI controller and enable the XHCI controller.

SeaBIOS has been tested on the board and boots an OS from a
flashdrive at SuperSpeed.
This also enables the top USB port on the 2-port stack, which goes
through a High Speed Inter-Chip port.  The HSIC port is only enabled
through the XHCI device.

Change-Id: Ic3dfc55028fa5e081a30819fe9596b1a9f57fd9c
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/6106
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Tested-by: build bot (Jenkins)
2014-06-26 01:32:28 +02:00
Kyösti Mälkki e3c65b97b4 gm45 boards: Switch to use DYNAMIC_CBMEM
Change-Id: Id19d31a2d114bb796b31ad61802d40c8608e4020
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6038
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-06-25 12:12:04 +02:00
Kyösti Mälkki 502e1dc7ca nehalem boards: Switch to use DYNAMIC_CBMEM
Change-Id: Ie4df2199e746de58c926f35bc9000752d399aa37
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6037
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-06-25 12:12:03 +02:00
Kyösti Mälkki 6455b01fe1 i945 boards: Switch to use DYNAMIC_CBMEM
Change-Id: I1bbcba086f841a90544b827ae807a3c351d19d21
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6036
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-06-25 12:12:02 +02:00
Kyösti Mälkki 56bd2005e6 emulation/qemu: Switch x86 to DYNAMIC_CBMEM
Change-Id: I00055064003c814b86fd1400d50bfd02fdfdf475
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6035
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-06-25 12:12:00 +02:00
Kyösti Mälkki d9cf38fdcb sandy/ivy boards: Switch to use DYNAMIC_CBMEM
Like with other more recent boards already using DYNAMIC_CBMEM,
the pointer to TOC is no longer stored in GNVS for ACPI.

Change-Id: If2e11294202c40793ec985e2c0c006bbfcd03d3d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6034
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-06-25 12:11:59 +02:00
Edward O'Callaghan c5fff75f68 pc80/mc146818rtc.h: Has X86 specific inlines without guards
PC80 header components are winding up in ARM builds with static inline
X86 specific code.

Change-Id: Ib23e70a34c478dc099b84b59a5234539cc2482e3
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6101
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-06-25 11:43:09 +02:00
Kyösti Mälkki 743a218a60 nehalem sandy ivy: Check cbmem_add() result for MRC data
In theory we could run out of CBMEM space so check the entry was added.
There is no interest to support builds without EARLY_CBMEM_INIT.

Change-Id: I68dd7c20e3d3692331aaafa2a692c5c0dfce95d5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6033
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-06-25 11:41:14 +02:00
Edward O'Callaghan b0cbb2cd17 drivers/intel/gma: Uninitialized var before if condition
The variable 'wait' is used uninitialized whenever 'if' condition is false
                if (val & DDI_BUF_CTL_ENABLE) {
                    ^~~~~~~~~~~~~~~~~~~~~~~~

Leading to an uninitialized use occurs here:
                if (wait)
                    ^~~~

Change-Id: I7d96bf1e33b9c4312d4a0ba8276e83d17d6cd070
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6052
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-25 11:38:33 +02:00
Edward O'Callaghan 502c3db939 include/pc80/mc146818rtc.h: Move include to top of file
Change-Id: I7640186702abac6fe116e3c750be08c958bc6cad
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6092
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-06-25 11:36:47 +02:00
Duncan Laurie 8d77402d3f intel/haswell: Report x32 memory as "x8 or x32"
There is only one bit for memory width reporting, either x16 or
other.  With x32 memory this code is reporting it as x8 so instead
report "x8 or x32" in this condition.

BUG=chrome-os-partner:23449
BRANCH=samus
TEST=emerge-samus chromeos-coreboot-samus

Change-Id: I2a7c49bcb8de19084947b9dc42b93140641886fc
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174120
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/6008
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-25 11:35:26 +02:00
Duncan Laurie 527b03a4d7 intel/lynxpoint: xhci: Update magic bits to new magic values
BUG=chrome-os-partner:22254
BRANCH=falco
TEST=emerge-falco chromeos-coreboot-falco

Original-Change-Id: I493a8cbbfdd958b855f6b4c01e03ee524be74c6e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/167050
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 226a66772768bf3c2f69e585984e52c0c270821f)

Change-Id: I800b02b511f9d188dd7a8e8d83139a8181346916
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/167312
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/6014
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-25 11:35:19 +02:00
Edward O'Callaghan a3119e5835 drivers/elog: Unmangle header include out of pre-proc cond
Change-Id: Ic4905d8a6908a30602382f5846f1dc2c0dbe2431
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6068
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-25 11:34:32 +02:00
Edward O'Callaghan b57fef9f3e src/ec: Sanitize headers and comment #endif pairings
Comment #endif /* FOO */ pairings.
Alphabetise headers and remove any #if CONFIG_ guards around them.

Background rational:
Remove guarding the inclusion of headers based on CONFIG_ options. This
*potentially* could hide issues such as functions being swapped from
under our feet, since different runtime behaviour could be declared with
the same function same name and type-signature. Hence, depending on the
header we happen to get may change runtime behaviour.

Change-Id: Ic61bdfb64d99f0e2998c6451ae6686915b7bb3d4
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6059
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-25 11:34:05 +02:00
Edward O'Callaghan 0ddb82671c src/console: Sanitize headers and IS_ENABLED usage
Alphabetise headers and remove any #if CONFIG_ guards around them.
Use #if IS_ENABLED(CONFIG_FOO) over #if CONFIG_FOO where applicable.

Change-Id: I2a616bcfb8470a1fa21c9e26271e81cca835272a
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6057
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-25 11:32:25 +02:00
Edward O'Callaghan 6c99250c3f device/pci_device.c: Sanitize headers
Change-Id: I6254f4ab767952cc8ff31bb462c7037b027442ba
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6079
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-25 11:32:24 +02:00
Edward O'Callaghan 618ddfeea5 device/{cardbus,agp}.h: Missing header for device_t type
Missing header for the ramstage version of device_t which is a struct
ptr.

Change-Id: Ie2a30b75ee1d0513397276b81e8df1d995707f6f
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6080
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-25 11:32:23 +02:00
Kyösti Mälkki b393fa09e5 AGESA S3: Fix ACPISCRATCH in CBMEM
After commit

  2ca2afe ACPI S3 support: Add acpi_s3_resume_allowed()

ACPISCRATCH region in CBMEM was no longer allocated, causing
AGESA platforms to fail S3 resume.

IS_ENABLED() did not evaluate true here with non-zero parameter.

Also avoid multiple defined defaults for HIGH_SCRATCH_MEMORY_SIZE.

Change-Id: Id99e4bee91581b8ac3d1ec44763b2d792b721832
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6093
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-06-25 06:23:07 +02:00