Commit Graph

15014 Commits

Author SHA1 Message Date
Duncan Laurie 86d937fb46 skylake: ACPI: Clean up pch.asl
Clean up the code in pch.asl:
- move all the C header includes into here instead of duplicated
in various ASL files included from here
- move the trap field definition into platform.asl with the method
- alphebetize the includes
- move gpio.asl include into pch.asl
- remove duplicate irqlinks.asl include from lpc.asl

BUG=chrome-os-partner:44622
BRANCH=none
TEST=emerge-glados coreboot

Change-Id: I51b1c5286fc344df6942a24c1dea71abf10ab561
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3ee9c4afa031191d275f0d3d40b2b15b85369b2f
Original-Change-Id: I3bae434ad227273885d8436db23e17e593739f77
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295903
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11530
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-08 11:16:42 +00:00
Duncan Laurie 0811230306 skylake: ACPI: Fix and clean up PCIE _PRT entries
Fix the code for PCIE _PRT entries to use an actual root
port number from the device instead of NVS that was never
initialized from zero.

BUG=chrome-os-partner:44622
BRANCH=none
TEST=build and boot on glados with pci=nomsi to ensure interrupts work

Change-Id: I76ff07d2bf7001aed504558d55cca9e19c692d7e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d43392199ec5f37150f2b13732924c47b8dc830c
Original-Change-Id: I1132f1dc47122db08d1b798a259ee9b52a488f5e
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295902
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11529
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-08 11:16:27 +00:00
Duncan Laurie 1bfbe7e72a glados: Update 4GB DIMM SPD for 1866
Enable 1866 timings in the 4GB Hynix SPD.

BUG=chrome-os-partner:44394
BRANCH=none
TEST=emerge-glados coreboot

Change-Id: Ibb84f77565d46894afe2153f5951e17a450413fc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f64d76a5f0b0095be96317674caf8542c3155423
Original-Change-Id: Ic5312176c21afc4569f723f5b7f00283b09262d7
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295174
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11528
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-08 11:16:11 +00:00
Alexandru Gagniuc 5c261229ae drivers/intel/fsp1_1: Take platform ID as a string, not integers
The platform ID is an 8 character ASCII string, so our config should
take it in as a string, rather than a set of two 32-bit integers.

Change-Id: I76da85fab59fe4891fbc3b5edf430f2791b70ffb
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11465
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2015-09-08 02:25:18 +00:00
Alexandru Gagniuc f55e6680b9 microcode: Unify rules to add microcode to CBFS once again
Now that cbfstool supports file alignment, we can use the conveniently
available <filename>-align handler, and remove the need to have a
separate rule in src/Makefile.inc just for adding the microcode.

We can also get rid of the layering violation of having the
CONFIG_PLATFORM_USES_FSP1_0 symbol in a generic src/cpu/ makefile.
Note that we still have a layering violation by the use of the
CONFIG_CPU_MICROCODE_CBFS_LOC symbol, but this one is acceptable
for the time being.

Change-Id: Id2f8c15d250a0c75300d0a870284cac0c68a311b
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11526
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-07 23:51:30 +00:00
Alexandru Gagniuc 9647094672 intel/sandybridge: Do not guard native VGA init by #ifdefs
We don't build-test with native VGA init, so if the code is broken by
a commit, we won't see it when it's guarded by #ifdefs. This has
already happened in the past. Instead of gurading entire files, use
the IS_ENABLED() macro, and return early. This at least enables us to
build-test the code to some extent, while linker garbage collection
will removed unused parts.

BONUS: Indenting some blocks also makes the difference between
framebuffer init and textmode init clearer.

Change-Id: I334cdee214872f967ae090170d61a0e4951c6b35
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11586
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-07 23:51:25 +00:00
Timothy Pearson 8ac492999a northbridge/amd/amdfam10: Use adequate size for HT speed limit field
Change-Id: Ib7ca49ffd53b0ae98a592b9fe8949dee2d9ae100
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11587
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-09-07 23:07:44 +00:00
Mono 2e4f83b164 intel i945: Fix native VGA initialization
Native VGA init no longer compiles  from commit:
* 7dbf9c6 edid: Use edid_mode struct to reduce redundancy

Tested on a single X60 machine.

This patch basically copies 11491 which does
the same for north/intel/sandybridge.

Change-Id: I0663f3b423624c67c2388a9cc44ec41f370f4a17
Signed-off-by: Axel Holewa <mono-for-coreboot@donderklumpen.de>
Reviewed-on: http://review.coreboot.org/11585
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-09-07 21:04:59 +00:00
Alexandru Gagniuc c241855240 north/intel/sandybridge: Fix native VGA initialization
Native VGA init no longer compiles  from commit:
* 7dbf9c6 edid: Use edid_mode struct to reduce redundancy

Change-Id: I51a4f4874ce77178cab96651eb7caf2edd862aa2
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11491
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-07 19:43:21 +00:00
Alexandru Gagniuc 2c482a969a intel: Do not hardcode the position of mrc.cache
The reason for hardcoding the position of the MRC cache was to satisfy
the alignment to the erase size of the flash chip. Hardcoding is no
longer needed, as we can specify alignment directly. In the long term,
the MRC cache will have to move to FMAP, but for now, we reduce
fragmentation in CBFS.

Note that soc/intel/common hardcoding of mrc.cache is not removed, as
the mrc cache implementation there does not use CBFS to find the cache
region, and needs a hardcoded address.

Change-Id: I5b9fc1ba58bb484c7b5f687368172d9ebe625bfd
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11527
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-07 17:40:32 +00:00
Stefan Reinauer 4460703f59 Drop "See file CREDITS..." comment
coreboot has no CREDITS file.

Change-Id: Iaa4686979ba1385b00ad1dbb6ea91e58f5014384
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/11514
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-07 15:54:50 +00:00
Alexandru Gagniuc 38bc916def cbfstool: Allow adding file with specific alignment requirement
Whenever we want to add a file to CBFS with a specific alignment, we
have to do two cbfstool invocations: one to find a place for the file,
and another to actually add the file to CBFS. Get rid of this nonsense
and allow this to be done in one step.

Change-Id: I526483296b494363f15dc169f163d93a6fc71bb0
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11525
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-07 08:44:06 +00:00
Alexander Couzens 3ed0d85d52 SeaBIOS: update stable release from 1.7.5 to 1.8.2
Several USB timing fixes for USB controllers on real hardware
Initial support for USB3 hubs
Initial support for SD cards (on QEMU only)
Initial support for transitioning to 32bit mode using SMIs (on QEMU TCG only)
SeaVGABIOS improvements:
 Added cursor emulation to coreboot native init vgabios (cbvga)
 Added support for read character calls when in graphics mode

Change-Id: Ic99f11dea4c87dbf3e9de4ce7f14064d0a083101
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: http://review.coreboot.org/11479
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-09-05 15:49:02 +00:00
Gerd Hoffmann 0bc3e325c9 qemu: fix vga driver build
Commit "7dbf9c6 edid: Use edid_mode struct to reduce redundancy" moved
some fields from "struct edid" to "struct edid_mode".  Adapt the bochs
and cirrus drivers to that change.

Change-Id: I9ec82a403d0264955d4b72496219036c7775c758
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/11502
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-09-05 15:48:03 +00:00
Aaron Durbin 037581542b symbols: add '_' to pci_drivers and cpu_drivers symbols
In order to prepare for more unification of the linker
scripts prefix pci_drivers, epci_drivers, cpu_drivers, and
ecpu_drivers with an underscore.

BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built different boards includes ones w/ and w/o relocatable
     ramstage.

Change-Id: I8918b38db3b754332e8d8506b424f3c6b3e06af8
Signed-off-by: Aaron Durbin <adubin@chromium.org>
Reviewed-on: http://review.coreboot.org/11506
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-09-05 15:36:23 +00:00
Aaron Durbin 541b567167 amd/thatcher: include .c files with the right path
The #include path during compilation already has '-I src'.
Don't encode the src part of a path.

BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built amd/thatcher while compiling romstage.c with C compiler..

Change-Id: If4fb1064a246b4fc11a958b07a0b76d9f9673898
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11512
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-09-05 15:26:37 +00:00
Aaron Durbin 649901e8e8 amd/geode_lx: make done_cache_as_ram_main global
Current code written in C is calling a function implemented
in assembly. However, the symbol's visibility is not set
for such usage. Of course this works because MAINBOARDDIR/romstage.c
is being processed into an assembly file currently.

BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built digitallogic/msm800sev while not changing romstage.c
     into an assembly file.

Change-Id: I84c3af0026f3f98bc64af007aa7cc196429f4e5f
Signed-off-by: Aaron Durbin <adubin@chromium.org>
Reviewed-on: http://review.coreboot.org/11511
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-09-05 15:26:25 +00:00
Aaron Durbin 4d3de7e328 bootstate: remove need for #ifdef ENV_RAMSTAGE
The BOOT_STATE_INIT_ENTRY macro can only be used in ramstage, however
the current state of the header meant bad build errors in non-ramstage.
Therefore, people had to #ifdef in the source. Remove that requirement.

Change-Id: I8755fc68bbaca6b72fbe8b4db4bcc1ccb35622bd
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11492
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-09-04 21:01:58 +00:00
Martin Roth c6a177d500 intel/common/firmware: Add common GBE rom support
Add support to the Intel common firmware Kconfig and Makefile.inc to
allow the Gigabit Ethernet (GBE) blob to be added to the final
binary.

Change-Id: Id5fab3061874dad759750b67d3339eb8c99a62d6
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10875
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2015-09-04 18:08:15 +00:00
Aaron Durbin 439356fabc x86: remove cpu_incs as romstage Make variable
When building up which files to include in romstage there
were both 'cpu_incs' and 'cpu_incs-y' which were used to
generate crt0.S. Remove the former to settle on cpu_incs-y
as the way to be included.

BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built rambi. No include file changes.

Change-Id: I8dc0631f8253c21c670f2f02928225ed5b869ce6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11494
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-04 15:09:32 +00:00
Aaron Durbin bc98cc66b2 bootmode: add display_init_required()
Some of the Chrome OS boards were directly calling vboot
called in some form after contorting around #ifdef preprocessor
macros. The reasoning is that Chrome OS doesn't always do display
initialization during startup. It's runtime dependent. While
this is a requirement that doesn't mean vboot functions should be
sprinkled around in the mainboard and chipset code. Instead provide
one function, display_init_required(), that provides the policy
for determining display initialization action. For Chrome OS
devices this function honors vboot_skip_display_init() and all
other configurations default to initializing display.

Change-Id: I403213e22c0e621e148773597a550addfbaf3f7e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11490
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-09-04 15:09:00 +00:00
Werner Zeh 5fc6f90ef7 mc_tcu3: Adjust gpio settings
Adjust gpio settings due to hardware change.

Change-Id: I4f493e5f46cbb9919c5b1a8ba294f8c34a07069a
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: http://review.coreboot.org/11489
Tested-by: build bot (Jenkins)
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2015-09-04 08:05:46 +00:00
Werner Zeh 69ddcf1b6e mc_tcu3: Extend hwinfo.hex and remove version.hex.
1. Update hwinfo.hex (add dummy data and update checksums).
2. Delete version.hex from mainboard directory. It can be added
   in site-local if needed.

Change-Id: I7af9c4a5f606b96177a8ed4e3edf52535f2f1ec7
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: http://review.coreboot.org/11484
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2015-09-03 08:20:35 +00:00
Alexander Couzens beb31d0cdc southbridge/ibexpeak: use new ssdt sata port generator
Drop old incomplete, broken and hardcoded sata.asl properties.
The new sata acpi generator only needs a proper defined device.

Change-Id: Id3eca5551a070dfdd6fa674e1d5b6627e28ab5a7
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: http://review.coreboot.org/9710
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2015-09-02 21:11:35 +00:00
Alexander Couzens 7bf47eecd6 southbridge/bd82x6x: use new ssdt sata port generator
Drop old incomplete, broken and hardcoded sata.asl properties.
The new sata acpi generator only needs a proper defined device.

Change-Id: I2be76097ebd27f2529e3fbbecefd314a0eea3cb0
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: http://review.coreboot.org/9709
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2015-09-02 21:11:10 +00:00
Duncan Laurie ef549a04c5 chromeec: Move keyboard backlight code into Chrome EC directory
Since more boards are starting to use the EC provided keyboard
backlight interface move the code to a common place and allow
it to get included in mainboards.

Change-Id: I3f307bbce1a96cdd1c8224b1e89a63d6fedef738
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: http://review.coreboot.org/11478
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-01 19:59:22 +00:00
Patrick Georgi ab5754da66 cbfstool: off-by-one on the gcc version that provides _Static_assert
According to https://gcc.gnu.org/gcc-4.6/changes.html it's only in gcc 4.6,
not 4.5, which I mistakenly believed.

Change-Id: I8212e7921bd9d1436a0ba491cbe6c4d473228956
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/11476
Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Tested-by: build bot (Jenkins)
2015-09-01 16:30:24 +00:00
Patrick Georgi 57c67e5aa5 cbfstool: guard _Static_assert
This isn't required for correct execution, and doesn't need to be tested
on every single compiler out there.

Since GCC < 4.5 has no idea about _Static_assert, hide it there. Our
build tests will make sure that the test is run before changes are
submitted to master.

Change-Id: I4141f4aa23b140d2d1017ca7b4dace5aa7db0c04
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/11475
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
2015-09-01 14:52:20 +00:00
Patrick Georgi 23aeaff41b cbfstool: implement decompression support for cbfstool extract
Change-Id: I5142b03d3c3e028eeb179f225848f762186f94a8
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/11363
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-01 14:52:02 +00:00
Patrick Georgi 61c822900e cbfstool: add decompression wrappers
... and document the interface.

Change-Id: I86a071a61fd6c1ef842f8ffe51f12f0cefdaf2fe
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/11362
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2015-09-01 14:51:53 +00:00
Patrick Georgi a71c83fa5c cbfstool: factor out parsing compression file attributes
cbfstool extract also needs it.

Change-Id: I8302bb18c5f797eb0a43ec4e4269790f3d49a896
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/11361
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-01 14:51:41 +00:00
Patrick Georgi c82725c5b9 cbfstool: support compressed files in cbfstool print
Display compressed and decompressed sizes, as well as the compression
algorithm used, when a compressed file is encountered.

Change-Id: I13c2332702c4a5bec379e1ebda72753e06f8e135
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/11359
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-01 14:51:29 +00:00
Daisuke Nojiri 8984a637c1 cbfstool: allow compression at file header level
Currently, compression is only allowed at subheader level (e.g. cbfs_stage,
cbfs_payload_segment). This change adds compression field to each file's
header so that any cbfs file can be compressed.

With the necessary additions in coreboot and libpayload, the following sample
code can load a compressed file:

	const char *name = "foo.bmp";
	struct cbfs_file *file = cbfs_get_file(media, name);
	void *dst = malloc(ntohl(file->uncompressed_size));
	dst = cbfs_get_file_content(media, name, type, file, dst);

cbfs_stage and cbfs_payload_segment continue to support compression at
subheader level because stages and payloads have to be decompressed to the load
address, which is stored in the subheader. For these, file level compression
should be turned off.

Change-Id: I9a00ec99dfc68ffb2771bb4a3cc5ba6ba8a326f4
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10935
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-01 14:51:19 +00:00
Patrick Georgi 2c61506630 cbfstool: add extended file attributes for cbfs_file
cbfs_file_first_attr(struct cbfs_file *) and
cbfs_file_next_attr(struct cbfs_file *, struct cbfs_file_attribute *)
help navigate through extended attributes.

cbfs_add_file_attr(header, tag, size) adds a new file attribute to
header.

Change-Id: I325965286c44f31abd95df684d340cebb0e68b75
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10934
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-01 14:51:09 +00:00
Martin Roth 4a666423c6 northbridge/intel/gm45/Kconfig: Remove IOMMU symbol choice
In the gm45 code, IOMMU is always selected to be enabled.  Instead
this patch removes the Kconfig symbol and its dependencies.  This leads
to the same effect without the need for the symbol.

The symbol is still used in the K8 code as it's not selected, simply
defaulted to being enabled, and one of the mainboards disables it.

Change-Id: Ibc5939cd1e297d497bf71b1787d852f7cc09a551
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11345
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2015-08-31 22:02:17 +00:00
Alexandru Gagniuc 3f2a945fb8 drivers/intel/fsp1_1/fsp_util.c: Use ALIGN_UP_macro
Change-Id: Iac4f275c14646b40ffe04fc5a6f6e1402cebfddf
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11464
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-31 19:45:15 +00:00
Alexandru Gagniuc 27fea06754 soc/intel: Fix dependency of CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
This depends on RELOCATABLE_RAMSTAGE, and shouldn't be selected if
its dependency is not activated.

Change-Id: I8e7efc3f87e105715fe3377ed306891f0d209979
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11473
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2015-08-31 15:38:05 +00:00
Aaron Durbin fbff301f78 util/cbmem: add -T option for machine parseable timestamps
In order to make analysis easier provide an option (-T) to
print timestamps in a parseable format:

ID<tab>raw timestamp<tab>time from previous entry<tab>description

BUG=chrome-os-partner:44669
BRANCH=firmware-strago-7287.B
TEST=Built and tested on glados. Used the following script:
cbmem  -T | awk 'BEGIN { FS="\t" } { tot += $3 } END { print tot }'

Change-Id: I06dc0487d1462b6a78924130f0ad74b0d787d3f8
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11471
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-31 13:58:02 +00:00
Aaron Durbin c49014e750 timestamp: add tick frequency to exported table
Add the timestamp tick frequency within the timestamp table so
the cbmem utility doesn't try to figure it out on its own. Those
paths still exist for x86 systems which don't provide tsc_freq_mhz().
All other non-x86 systems use the monotonic timer which has a 1us
granularity or 1MHz.

One of the main reasons is that Linux is reporting
/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_max_freq as the true
turbo frequency on turbo enables machines. This change also fixes
the p-state values honored in cpufreq for turbo machines in that
turbo p-pstates were reported as 100MHz greater than nominal.

BUG=chrome-os-partner:44669
BRANCH=firmware-strago-7287.B
TEST=Built and booted on glados. Confirmed table frequency honored.

Change-Id: I763fe2d9a7b01d0ef5556e5abff36032062f5801
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11470
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-31 13:55:28 +00:00
Aaron Durbin 60391b65fd imgtec/pistachio: remove timestamp_get() implementation
As pistachio already provides timer_monotonic_get() let the
generic timestamp_get() use that instead of having around
another implementation of timestamp_get().

BUG=chrome-os-partner:44669
BRANCH=None
TEST=None

Change-Id: Iaa6db49f0055b7c2ef116f41453f838093e516e0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11469
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-08-31 13:55:13 +00:00
Aaron Durbin 107d1fb137 armv7/arm64: remove timestamp.c
The src/lib/timestamp.c already has an implementation using
timer_monotonic_get() for timestamp_get(). Use that instead
of duplicating the logic.

BUG=chrome-os-partner:44669
BRANCH=None
TEST=None

Change-Id: If17be86143f217445bd64d67ceee4355fa482d39
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11468
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-08-31 13:55:03 +00:00
zbao 4a2fc3e6f0 AMD bettong: Fix the PCIe lane map
Change-Id: Ieaed5cf76c6f0a6a121e6add731d5c1e1528dfc7
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/11375
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-31 06:46:26 +00:00
zbao d5b778d269 AMD Bettong: Set the USB3 port as unremoveable.
Without this change, if one USB3 device is attached when
the board is power up, the USB3 port can not be used.

Change-Id: I98628975000c7d56b1540c2b321d580ace1ef70e
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/11377
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-31 06:45:58 +00:00
zbao 418026f63f AMD Bettong: Lower the TOM to give more MMIO space
Change-Id: Idf28faa26a7ea5e94495af5ff027309df444766e
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/11376
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-31 06:45:35 +00:00
zbao d22b9ea1cb buildgcc: Show the exit status of wget if downloading fails.
Change-Id: Ie3a44c6db9c9c186c52b4743334266ec5411ba8a
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/11472
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-31 06:45:13 +00:00
zbao ff3f15cd4d buildgcc: remove getopt when doing clean.
Change-Id: I9f59a00e735f39df813b2216290da62eea3c595d
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/11372
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-31 06:44:57 +00:00
Alexandru Gagniuc 1cb1c924c5 soc/intel/braswell/Kconfig: Remove ENABLE_MRC_CACHE Kconfig
This option was removed in the following commit:
* 80f5d5b fsp1_1: remove duplicate mrc caching mechanism

Change-Id: I08ef4fc6029cc066e4f7b9c82b6b187a9794afdb
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11462
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-31 03:17:08 +00:00
Alexandru Gagniuc 681012ab3d drivers/intel/fsp_1_1: Remove useless #ifndef/#error pairs
The #error messages only say that "CONFIG_* must be defined", which
conveys no more information that the compiler or assembler failing
when it encounters an undefined CONFIG_* symbol.

Change-Id: I6058474d4cd454cfc20290650425d379f388abd9
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11461
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-31 03:17:02 +00:00
Damien Zammit 9c98664480 inteltool: Add Intel 4-Series chipset detection
Previously, X4X was incorrectly named because it provides
support for SKUs within XX4X range.  This is renamed.

This patch provides support for all X4X SKUs according to
datasheet Intel 4 Series Chipset Family Specification Update,
namely: Q45, Q43, P45, P43, G45, G43, G41 and B43 (both versions).

Tested on Gigabyte GA-G41M-ES2L

Change-Id: I032265e80d9ca51e2fef29201280832ea3210a0b
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: http://review.coreboot.org/11245
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-08-30 18:05:18 +00:00
Alexandru Gagniuc fdbc1af5e2 Kconfig: Remove EXPERT mode
After much consideration, and many years of an EXPERT mode sitting
almost completely unused, we've seen that it doesn't work for us.
There is no standard on what constitutes EXPERT, and most of
coreboot's options Kconfig are expert-level.

We even joked that not selecting "EXPERT" should prevent coreboot
from compiling:

@echo $(shell whoami) is not permitted to compile coreboot

Change-Id: Ic22dd54a48190b81d711625efb6b9f3078f41778
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11365
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2015-08-30 07:50:47 +00:00