Change-Id: I7cf47a16928436734df29af951f987db9cf9530d
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/6847
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
As a first step towards removing hardcodes from the FUI support,
change the haswell call to i915_lightup to panel_lightup, and pass the
intel_dp * as a parameter. Get rid of the scalar arguments and make
them part of intel_dp. Get rid of file-scope variables and use the
ones in the intel_dp struct. In falco, use functions that peppy
uses. Drop slippy support for FUI, it's a dead board; if this is ok
I'll remove the files next.
And, incidentally, fix the broken RGBX constant and change it to BGRX.
Change-Id: I46ef5a9ed8433382d042066ee3542af04cfc319a
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://chromium-review.googlesource.com/174932
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
(cherry picked from commit 1e1ed410b445c8e2b7411e163d9d6f61499dc3f6)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6833
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
It's time to start cleaning up the falco graphics code, but it needs
to have its own files, not slippy's.
Change-Id: I7dbe27eafbf247b5c7806819bf0059d8b10e842c
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://chromium-review.googlesource.com/172501
Tested-by: Ronald Minnich <rminnich@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 262a0c16a39871d14972a92bff2dbc24de2ca3f0)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6832
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
- GPIO29 is no longer connected so we don't need the SMI workaround
on the entry to sleep states.
- Disable touchscreen wake source until the kernel driver is working
so it does not wake immediately.
- Update a few GPIOs and disable the codec for now as it is leaking
into the 1.8V DDR rail.
Change-Id: Ia67b17eb4a097627befd8f39aadc939da1bf3d40
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174122
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 0fdc9a83a434378499f825d072ce0adba5ffda59)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6829
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The LPDDR3 memory is x32 and dual rank with 14 row bits.
In addition the memory is actually elpida, even though
they are owned by micron it is confusing to label it as such.
And the ram strap options were inverted from what I expected
so the memory table needs to be updated.
Change-Id: Ia29a23e8140d884fb84f940806f041b40562aab9
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174121
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 0d63d36b8035165f95db798ed40488519e622a65)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6828
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
SMI1 is being written to but never read from.
Change-Id: I82c0800713e3093eb1317b5e1f6f228771134857
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/6808
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Create a new mainboard based on the AMD DB-FT3 development board
(Olive Hill) using an AMD Steppe Eagle processor. The actual DB-FT3
and DB-FT3b mainboards are identical except for the soldered-down
SoC device. The new AMD DB-FT3b development board (Olive Hill+)
features:
* Mini-ITX form factor
* 2x DisplayPort
* 1x VGA
* Integrated Realtek RTL8111-compatible Ethernet
* 2x USB 3.0 ports
* 2x USB 2.0 externally-accessible ports
* 2x USB 2.0 internally-accessible ports (via headers)
* micro LPC header
* Integrated platform security processor
* 2x Full-size DDR3 DIMM support (1 channel)
* Realtek ALC272 HD audio
* 2x SATA ports
* 1x SD card slot
* 1x PCIe (x4) slot
* 1x mini-PCIe slot
* 8-pin programming header
Eliminate the extraneous headers included in PlatformGnbPcie.
BiosCallOuts normally has a bunch of extraneous references to the
mainboard name. Rather than correct the spelling of a bunch of
instances, just get rid of them.
For the most part, use the Olive Hill ACPI definitions since the
DB-FT3b board ("Olive Hill+") and Olive Hill are the same board
with different processors.
Change some function prototypes for functions without parameters
to void instead of AGESA's VOID. There are no parameters for
these functions, so there is no real reason to use VOID.
S3 and fan control are not supported. HD audio is not working.
Change-Id: I794d7a8f4f948346cfe7cbd443c9aed5f70c99ed
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/6681
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <gaumless@gmail.com>
Checked by comparing binaries and seeing no differences other than
build info.
Change-Id: Ie702c540a18b50d6da0379f7c4e65adf3e4f18d4
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/6819
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Not referenced anywhere.
Change-Id: I6529f2ecbc34a2fa9ca720fea1224670eb98bdcd
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/6815
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
There is some magic new SPD SDRAM type 241 to indicate LPDDR.
I cannot find it specificed in any JEDEC document but it is
what the reference code uses.
Change-Id: I21d7a943784435cb336ecdba7ca5eac0bf5fcd92
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/171900
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 0a1385515c62fd1e534b12568df8aaf2170e06f4)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6777
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Change-Id: I7b9b91519d87d70405b57920b3f1ab98c50526d1
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/6810
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
OEM strings should not be handled by mobo code but by common code with strings
collected from all devices.
Change-Id: Ibde61a1ca79845670bc0df87dc6c67fa868d48a9
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/6788
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Tablets have different mainboard version than laptop variants.
Change-Id: I77a1e2b50d30dcf3fa064e0c378ceca7ccf96e89
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/6785
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
This interrupt needs to be specified in the MADT before it can
be used by the kernel driver.
Change-Id: Ic920a792a203cb06cd4529815680584a21532106
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/171902
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit a330fddb62cb6346ad66ceb5b5c32b66aecd81e2)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6778
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Add the coreboot board files for samus
- Based on Bolt
- GPIO setup based on 0.91 schematic
- Support both memory types
- No HDA verb table for this platform
- Some GPIO interrupts are shared and need to be passed to OS
Change-Id: I8dbd7639456c631a0115b03a493d94b5e2361ab5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/171694
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 249a74c628264e3d4ce754803ede31238404b4d5)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6775
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Move (and rename to make it clearer) the function that computes display
parameters from the dpcd and edid.
Change-Id: Idfbb56fd312b23c742c52abca1a34ae117a8fece
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://chromium-review.googlesource.com/171366
Reviewed-by: Furquan Shaikh <furquan.m.shaikh@gmail.com>
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
(cherry picked from commit 8f2b3bafee7cb05db8fae1c52fc9e1ee64e5e35d)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6768
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
The Exynos family and most ARM products are SoC, not just CPU.
We used to put ARM code in src/cpu to avoid polluting the code base for what was
essentially an experiment at the time. Now that it's past the experimental phase
and we're going to see more SoCs (including intel/baytrail) in coreboot.
Change-Id: I5ea1f822664244edf5f77087bc8018d7c535f81c
Reviewed-on: https://chromium-review.googlesource.com/170891
Tested-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Commit-Queue: Hung-Te Lin <hungte@chromium.org>
(cherry picked from commit c8bb8fe0b20be37465f93c738d80e7e43033670a)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6739
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The code to set the graphics translation table has been in the
mainboards, but should be in the northbridge support code.
Move the function, give it a better name, and enable support for > 4
GiB while we're at it, in the remote possibility that we get some 8
GiB haswell boards.
Change-Id: I72b4a0a88e53435e00d9b5e945479a51bd205130
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://chromium-review.googlesource.com/171160
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan.m.shaikh@gmail.com>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
(cherry picked from commit d5a429498147c479eb51477927e146de809effce)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6741
Tested-by: build bot (Jenkins)
Peppy had some issues with FUI. We decided it was time to create
peppy-specific gma.c and i915io.c files. Using yabel and the i915tool,
we generated a replay attack, then interpolated against the slippy
i915io.c to get something working.
Also, in preparation for moving code out of the mainboard gma.c to
generic driver code, we got rid of some hardcodes in the mainboard
gma.c that have no business being there. The worst were the
computation of gmch_[m,n] and it turns out that we had some
long-standing bugs related to confusion about 'bpp'. I've killed the
word bpp everywhere I could because there are at least 3 things that
correspond to bpp. We now have framebuffer, pipe, and panel bpp. The
names are long because I want to avoid all the mistakes we've all been
making in the last year :-) Sadly, that means a lot of changes not just
peppy-related, but they are simple and in a good cause.
The test pattern generation is driven by a global variable in
mainboard/peppy/gma.c. I've found in the past that it's very useful
to have a function like this available, as one can activate it while
using a jtag debugger: halt at the right place in ramstage, set the
variable to 1, continue. It's not enough code to worry about always
including.
The last hard-codes for M and N registers are gone, and the function
to set from generic intel_dp.c code works. To avoid screen trash on a
dev mode boot, which we liked but nobody else did :-), we now take the
time to put a pleasing background color that sort of doubles as a
power LED.
Rough timing is ramstage start is at 2.2, and dev setup is done at
3.3. These new platforms are depressingly slow to boot. Rom init alone
is taking 1.9 seconds. 13 years ago it was 3 seconds from power on to bash
prompt. These CPUs are at least 10x faster and take much longer to get going.
Future work, once we get this through, is to move more functions to the
intel driver, and combine the mainboard i915io.c into the mainboard gma.c.
That separation only existed because i915io.c was generated by a tool, and it
had lots of ugliness. Most ugliness is gone.
Old-Change-Id: I6a6295b423a41e263f82cef33eacb92a14163321
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/170013
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
Reviewed-by: Furquan Shaikh <furquan.m.shaikh@gmail.com>
(cherry picked from commit 8cdaf73e3602e15925859866714db4d5ec6c947d)
snow: Fix a typo in devicetree.cb that was breaking the snow build.
A typo in a recent change broke the snow build.
Old-Change-Id: I93074e68eb3d21510d974fd8e9c63b3947285afd
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/171014
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 154876c126a6690930141df178485658533096d2)
Squashed a fix into the initial patch and updated nehalem/gma.c
to have a non-static gtt_poll.
Change-Id: I2f4342c610d87335411da1d6d405171dc80c1f14
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6657
Tested-by: build bot (Jenkins)
override default ivy VGA_BIOS_ID
add model & part number
Remove ARCH_X86 as is in,
fd33781 Move ARCH_* from board/Kconfig to cpu or soc Kconfig.
Change-Id: I61dc6434de7af2d8672f784df87a8b9d3f0fb068
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/6759
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
This disables the blink hardware as it seems to be in the dump. This is
safer as it does not rely on 0 as the reset value when '0x00040000' is
the default according to the util/inteltool. As seen:
gpiobase+0x0018: 0x00040000 (GPO_BLINK) DIFF
Change-Id: Ia1fde108bf3752484f5e991600c435f776af0ced
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6436
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Use defines of offsets rather than hard coded values.
Change-Id: Id2471cd22aa402d74163473e48f86af9789cdaa7
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6435
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
SATA Port documentation
PCIe unused ports and documentation
T520 have no keyboard backlight
Change-Id: I517ff8519ea22a9a7a9b6e3136efd15d4a0f8fc4
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/6743
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Thinkpad T520 ExpressCard Slot PCIe lanes are connected to port 4.
Tested with Serial Port Card. Information read from schematic / lspci
Change-Id: I459943d427578d135f9aed1aa66da269ddfeee87
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/6735
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Clean up both ram and rom stage support and fix board to match.
Change-Id: I55e3e7338c0551f0fb663eb9707f16ecdc1aca35
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6509
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Compile romstage component as link-time symbols. Pass CONFIG_TTY0_BASE
as argument instead of hard coding and playing funny business with the
pre-processor. Fix board to match.
Change-Id: If6d0d5389bd4e7765bb6056cf488c94fd45915c2
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6463
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
