Commit Graph

8018 Commits

Author SHA1 Message Date
Patrick Georgi 72a2eaf4d5 Rename mainboard_smi.c to smihandler.c
This mirrors the naming convention of handlers in
northbridge and southbridge.

Change-Id: I45d97c569991c955f0ae54ce909d8c267e9a5173
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/2058
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-01-03 19:33:01 +01:00
Ronald G. Minnich 64b364d1ec Add the push default to 'make gitconfig'
It's too easy to forget this and it's kind of important, so Just Add It.

Change-Id: Ic7ab7658425a98d5d435bfef46f89cc6a56c7284
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2096
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-01-03 19:32:29 +01:00
David Hendricks ec8d35fe91 armv7: pass bootblock offset from Kconfig into cbfstool
This replaces a somewhat useless calculation used earlier (which
always evaluated to 0) with an offset to specify the location
of the Coreboot bootblock.

Change-Id: Ib85aaccf138cebeb6bf8aedf82308861206dff48
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2094
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-03 06:46:36 +01:00
David Hendricks 4c2245eb67 snow: Stuff to support building image with BL1
This patch does two things which will take effect in follow-up
patches:
1. Add an intermediate Makefile rule for dd'ing BL1 into the
   coreboot.rom pre-image. This is modeled after a similar hack
   for the bd82x6x southbridge.
2. Add a Kconfig variable, BOOTBLOCK_OFFSET, which will be used to
   pass the bootblock offset into cbfstool.

Change-Id: I89da255dc903c387b754b06a11bb3439035ead87
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2093
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-03 06:46:09 +01:00
David Hendricks 454856b274 add user-specified offset when creating armv7 cbfs image
The "offs" provided on the command-line was not taken into account
when creating an image for armv7...

Change-Id: I1781bd636f60c00581f3bd1d54506f0f50bb8ad0
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2092
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-03 06:45:25 +01:00
David Hendricks 45256b3bfc Add (hacked-up) s3c24x0_i2c files
These are needed for communicating with the PMIC on Snow. We'll
tidy them up as we go along...

Change-Id: I197f59927eae0ad66191862d052de2a8873fb22f
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2078
Tested-by: build bot (Jenkins)
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2013-01-03 06:42:16 +01:00
David Hendricks d3c7530908 import SPL files for board_i2c_{claim,release}_bus()
This imports SPL (second phase loader) files from U-Boot. Most of the
content of these files will eventually go away since they're fairly
U-Boot specific. For now they are here to make Jenkins happy.

Change-Id: Ib3a365ecb9dc304b20f7c1c06665aad2c0c53e69
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2081
Tested-by: build bot (Jenkins)
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2013-01-03 06:41:55 +01:00
David Hendricks 8583ac390a armv7: create init.S for early ARMv7 init
The old start.S file did a lot of work and had AP-specific #ifndef's.
The new init.S will eventually contain only bare minimum generic ARM
code for use by the bootblock. Processor-specific stuff and things
that take place later in the boot process should go elsewhere.

Change-Id: I7db0a77ee4bbad1ddecb193ea125d8941a50532b
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2083
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-03 06:41:36 +01:00
Stefan Reinauer 1e0e55615f cbmem utility: support command line options
The tool could print much more useful information than
just time stamps, for example the cbmem console on systems
that don't have a kernel patched to support /sys/firmware/log.

Hence, add command line option parsing to make adding such
features easier in the future.

Change-Id: Ib2b2584970f8a4e4187da803fcc5a95469f23a6a
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2091
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: build bot (Jenkins)
2013-01-03 01:09:50 +01:00
Stefan Reinauer 2c3f2609ca Fix strcpy()
'nough said. It was broken since 2006.

Change-Id: I312ac07eee65d6bb8567851dd38064c7f51b3bd2
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2062
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-01-03 00:56:59 +01:00
Aladyshev Konstantin f50fbe82ad AGESA: Use `Flag=AGESA_SUCCESS` instead of `TRUE` in DMI related functions
Success return value in DMI functions GetDmiInfoMain(..) and GetType4Type7Info(...) of AGESA vendorcode is "Flag = TRUE".

This results in a failure of init late function:

    "agesawrapper_amdinitlate failed: 1"

It happens because TRUE = 1 = AGESA_UNSUPPORTED.

Replacing TRUE with AGESA_SUCCESS (= 0) fixes this problem.

Only family f15tn does not have such bug.

This patch just replaces TRUE with AGESA_SUCCESS, but maybe all DMI functions should be copied from Trinity family?

Tested on Supermicro H8QGI board with 4 AMD Opteron 6234 processors (f15).

Change-Id: I51bf91333c088a825b92d4a44d1ebe4380c8026c
Signed-off-by: Aladyshev Konstantin <aladyshev@nicevt.ru>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2070
Reviewed-by: Marc Jones <marcj303@gmail.com>
Tested-by: build bot (Jenkins)
2013-01-02 20:37:16 +01:00
Aladyshev Konstantin c855dce825 Supermicro H8QGI: Pass callout pointer to AmdReadEventLog function
I have issues when AmdReadEventLog function tries to use BiosCallouts interface.
So it is necessary to provide callout pointer to this function.

Change-Id: I4080e5f07d5d28c41688b2a7deff944b7a0f7bf7
Signed-off-by: Aladyshev Konstantin <aladyshev@nicevt.ru>
Reviewed-on: http://review.coreboot.org/2064
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
2013-01-02 20:19:08 +01:00
Denis 'GNUtoo' Carikli 34746a9c48 rs780: Implement `rs780_internal_gfx_disable` and add .disable pcie_ops
That code will be used to disable the internal GFX card and enable the
external PCIe card.

The following lines from function `rs780_internal_gfx_enable()` are
taken and reversed.

	/* Disable external GFX and enable internal GFX. */
	l_dword = pci_read_config32(nb_dev, 0x8c);
	l_dword &= ~(1<<0);
	l_dword |= 1<<1;
	pci_write_config32(nb_dev, 0x8c, l_dword);

It has been tested on the M4A785T-M with the following card inside the
PCIe 16x slot:

  02:00.0 VGA compatible controller: nVidia Corporation GT218 [GeForce 210] (rev a2)

Change-Id: I7bd412b987fde98c97464175e2c7a384a8f0fb84
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2065
Tested-by: build bot (Jenkins)
2012-12-30 22:45:56 +01:00
Denis 'GNUtoo' Carikli 9a0e3e2fc2 M4A785T-M: Add support for external GFX.
This commit enables the external graphics card.
In order to work, the internal graphic card has to be
  disabled, that is done in src/device/device.c through:
  vga_onboard->ops->disable(vga_onboard);
  which calls the RS780 disable operation introduced in the following
  commit: "rs780: add .disable pcie_ops"

This commit was tested with and without the following card:
  02:00.0 VGA compatible controller: nVidia Corporation GT218 [GeForce 210] (rev a2)

Thanks Aladyshev for the pointer(in the #coreboot IRC channel on Freenode servers):
  Dec 20 19:43:32 <Aladyshev>	If you list your internal card in devicetree.cb,
  coreboot will distinguish external and internal VGA and choose external one

Change-Id: I92e59dffd158db096a6e99d1ef6e2e248fef933c
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/2067
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-30 03:25:33 +01:00
Marc Jones 6c6b2e8cba Add AMD Hudson blobs by CONFIG_REQUIRES_BLOBS dependency
If a 3rd party blob option is selected, make sure that it makes the
user select CONFIG_USE_BLOBS as otherwise the build will fail.

Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: I04429f23137946525c8577dd9c979bd4a0d17cdc
Reviewed-on: http://review.coreboot.org/2080
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-29 18:35:14 +01:00
David Hendricks 6c212ac483 remove obsolete include paths from INCLUDES
Change-Id: I621fd49b1f1b96ef388c61ff1abc2130ad2163a5
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2082
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-29 15:35:29 +01:00
David Hendricks f4c35083d0 import i2c header from u-boot
This just imports a header. We may wish to modify the i2c interface
and/or unify it with the smbus interface we currently have.

Change-Id: I314f3aef62be936456c6c3e164a3db2c473b8792
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2079
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-29 15:34:26 +01:00
David Hendricks e293440faa corrections for MAX77686 config variable
Fix some minor discrepancies which prevented the MAX77676 from
getting compiled in properly.

Change-Id: Ib29136da6c15a4bdb24926a91729431c507cd209
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2076
Tested-by: build bot (Jenkins)
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-29 15:33:53 +01:00
David Hendricks f1dfb2eb94 move iRAM config variable to exynos5250 Kconfig
Since these don't seem very generic and depend on the BL1, let's
move them to the CPU-specific Kconfig.

Change-Id: I33059b7db30d35a1853918a580f312e50a3499fa
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2077
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-29 15:33:17 +01:00
David Hendricks 37a8516370 Simplify romstage.ld for armv7
This is still a work-in-progress, but it seems to work better than
before and is less complicated...

Change-Id: I6f730d017391f9ec4401cdfd34931c869df10a9e
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2041
Tested-by: build bot (Jenkins)
2012-12-29 15:25:05 +01:00
Aladyshev Konstantin 32675175ef Supermicro H8QGI: Add onboard VGA to devicetree.cb
Supermicro H8QGI has integrated Matrox G200 16MB DDR2 graphics.
List it in devicetree.cb to mark it as onboard VGA to coreboot.
This change makes menuconfig option "Use onboard VGA as primary video device" work.

Change-Id: Ia6b9f60e3ae705689f22babd544ad6e628a85df1
Signed-off-by: Aladyshev Konstantin <aladyshev@nicevt.ru>
Reviewed-on: http://review.coreboot.org/2042
Tested-by: build bot (Jenkins)
Reviewed-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-12-28 21:23:44 +01:00
Aladyshev Konstantin c94e8cf2e1 Supermicro H8QGI: fix bus_sp5100[] clear in get_bus_conf.c
Fix little mistake in get_bus_conf code

Change-Id: I8c09e501082caa0a20266b007c0744630a356de0
Signed-off-by: Aladyshev Konstantin <aladyshev@nicevt.ru>
Reviewed-on: http://review.coreboot.org/2046
Tested-by: build bot (Jenkins)
Reviewed-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-12-28 21:21:52 +01:00
Aladyshev Konstantin 3d63b0a965 BiosCallOuts: Replace REQUIRED_CALLOUTS define with flexible variable
Size of BiosCallouts[] struct can be calculated as:

        CallOutCount = sizeof (BiosCallouts) / sizeof (BiosCallouts [0]);

There is no longer need for REQUIRED_CALLOUTS define.

Originally that change was done for AMD Persimmon in

        commit d7a696d0f2
        Author: efdesign98 <efdesign98@gmail.com>
        Date:   Thu Sep 15 15:24:26 2011 -0600

            Persimmon updates for AMD F14 rev C0

without deleting the define. This was ported to some of the other
boards and for some the define was not removed.

The AMD Inagua, Parmer and Thatcher boards were already adapted but
the define was left in. So just remove it for those.

Tested on Supermicro H8QGI.

Change-Id: Ia09795579a1170fa20ab94a30feb1af6821153d2
Signed-off-by: Aladyshev Konstantin <aladyshev@nicevt.ru>
Reviewed-on: http://review.coreboot.org/2049
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin@se-eng.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-12-28 21:19:42 +01:00
Zheng Bao b01097e0fe USBDEBUG: Enable the EHCI in AMD Southbridge
Since SB800, USB2.0 debug port is dev 0x12, func 2.

Change-Id: Ie0e33cb2f0833b0baeef81323e1a0634242fbe55
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1880
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-12-28 21:16:42 +01:00
David Hendricks ceb82da99f add a return type to test function used by xcompile
This fixes a minor bug that could cause testcc to fail unexpectedly.

Change-Id: Ib75d343104b6937682c05acf5232596aac83f105
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2068
Tested-by: build bot (Jenkins)
2012-12-21 20:18:31 +01:00
Aladyshev Konstantin ec3daf7e08 Supermicro H8QGI: Fix routing from 16 to 55 in ACPI table
H8QGI board has 2 IO-APICS with 56 IRQ’s:

IOAPIC[0]: GSI  0-23   - SB700 southbridge
IOAPIC[1]: GSI 24-55   - RD890 northbridge

`gDefaultApicDeviceInfoTable[]` structure in northbridge code

    vendorcode/amd/cimx/rd890/nbIoApic.c

has IO-APIC interrupt mapping for HT and IOMMU set to last 31
IRQ pin (24+31=55).

    CONST APIC_DEVICE_INFO gDefaultApicDeviceInfoTable[] = {
    // Group  Swizzling   Port Int Pin
      {0,     0,          31},   //HT
      {0,     0,          31},   //IOMMU
    […]

Also the same value (55) can be found in original Supermicro BIOS ACPI DSDT.

Change-Id: Ie26da1f773716d1b7f5f5f884050ae799afc0b7e
Signed-off-by: Aladyshev Konstantin <aladyshev@nicevt.ru>
Reviewed-on: http://review.coreboot.org/2047
Tested-by: build bot (Jenkins)
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-21 15:43:38 +01:00
Stefan Reinauer 7299c139c5 PDcurses: Delete automatically created (and unused) files
Change-Id: Iefe0872d36c3a5d8ef42e62325838b7f09b389d2
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2034
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
2012-12-20 14:46:29 +01:00
Patrick Georgi 69e3de3393 libpayload: Another usb fix
Change-Id: I91b18fadbf17562f8b48e233631653f2a18c037c
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/2063
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-12-20 09:31:01 +01:00
Stefan Reinauer e09f7ef00a Add back dummy free()
GNU CC coverage needs free() and it's highly desirable to leave
the code as genuine as possible.

Change-Id: I4c821b9d211ef7a8e7168dc5e3116730693999c6
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2051
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2012-12-19 22:37:43 +01:00
Patrick Georgi 5fa7ea419b libpayload: fix USB
A "far" modifier sneaked into the USB driver, but gcc
doesn't understand it.

Change-Id: I5c67bd55eabce467e1aa107c95c1db2518af7b0e
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/2059
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-12-19 20:53:36 +01:00
Patrick Georgi ebb89e3a8c No need to contact AMD for firmware anymore
We ship it in the 3rdparty repository.

Change-Id: Ida52bc7e813f8468910c4ea7838ebb863c52b88a
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/2060
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2012-12-19 20:13:41 +01:00
Patrick Georgi 7a33442159 Remove colors from build system output
While "payload none" is undesirable for instant flashing,
assume that it was a conscious user choice.

(more immediate: jenkins isn't happy with escape sequences)

Change-Id: I9958b34a037b4d10bb7dba893335a63917623a70
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/2055
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-19 17:00:20 +01:00
Anton Kochkov c62b69cd02 libpayload: improved UHCI TD debugging
Improved USB debugging for EHCI by enhacing dump_td
to dump all chain information

Change-Id: I8c667b43e09c39ff12aafbd779474efd652bd80f
Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com>
Reviewed-on: http://review.coreboot.org/2054
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.huber@secunet.com>
2012-12-19 15:19:34 +01:00
Anton Kochkov cf7b63ff65 libpayload: improving OHCI TD/ED debugging
Improving USB debugging for OHCI by enhacing dump_td
and adding dump_ed function to dump all chain information

Change-Id: Ia8b2a9b53e79b1f280fd12ea0d9233fc875e0b57
Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com>
Reviewed-on: http://review.coreboot.org/2056
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.huber@secunet.com>
2012-12-19 15:19:24 +01:00
Stefan Reinauer ea9a1f6017 Get stdint.h in sync between ARMv7 and x86
- add s8, s16, s32 types to x86

Change-Id: Ib9c260fc4f72029492f2d935dbb822cc3ff83cc4
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2050
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2012-12-19 00:20:33 +01:00
Dave Frodin 5056b6e612 libpayload: Check if serial console h/w is present before using
The serial_io_havechar() and serial_io_getchar() functions will
always see keystrokes available if the serial hardware isn't
actually there. We will still output chars to non-existant
hardware to allow virtual hardware to capture them.

Change-Id: I04e85157b6b7a185448abab352b5417a798a397a
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/2040
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-12-18 19:59:59 +01:00
Dave Frodin 6bf11cf50c libpayload: Use usb_debug() to show USB messages
Previously printf()'s were used to show USB messages
which results in lots of USB information being shown
when it isn't needed. This will now use the usb_debug()
printing funtion that already exists in usb.h.

Change-Id: I2199814de3327417417eb2e26a660f4a5557cb9f
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/2044
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-12-18 19:59:22 +01:00
Dave Frodin 8024b65550 libpayload: Update configs/defconfig file
Several settings have been added to the config without any
changes to the default settings file.

Change-Id: Iaf9259d77fb3c4645fc68bc0108de79c0298f0a1
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/2039
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-12-18 15:05:36 +01:00
Martin Roth c5f4926cb9 Fix a compare against undefined variable in acpi.c
Initialize the pointer fadt to NULL to prevent a later comparison
(if (fadt == NULL)) when the pointer had the *possibility* of never
having been initialized.

Change-Id: Ib2a544c190b609ab8c23147dc69dca5f4ac7f38c
Signed-off-by: Martin Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/2037
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)
2012-12-15 03:49:08 +01:00
Stefan Reinauer 9f04317263 libpayload: add kconfig.h
This implements the linux kernel's macros to handle
boolean CONFIG_ variables more easily.

Change-Id: I595f9db652d019fe72e231111258ec609bec9d4e
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2036
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-14 23:59:05 +01:00
Stefan Reinauer 8af0d03fd4 libpayload: Initial ARMv7 port
This compiles, but it's not tested yet.

Change-Id: I2f73a814649aa36c39af3e77cefd8a968671f5c0
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2035
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-14 22:29:48 +01:00
Stefan Reinauer f6935a006a libpayload: rename i386 to x86
Change-Id: Ia9170bd3d04e76dbf9321ca7ea4be23b5e468d21
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2033
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-14 22:29:17 +01:00
Martin Roth 9aaf7d17bb Fix broken scan-build
Adding support for the multiple architectures broke the scan-build
option.  The new CC setting needed to be wrapped and not run again
when doing the scan-build second pass.

Change-Id: Ieb418f51d44803308040926a4154fb5fdc3ba67f
Signed-off-by: Martin Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/2031
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-12-14 22:21:10 +01:00
Zheng Bao bb71c91db1 AMD S3: Rename generated s3.rom for make clean
Add prefix coreboot_ to let make clean find it and delete it.

Change-Id: Ieba9c0e7ca3d2afec311d64159b22746ba5825c4
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/2029
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-12-14 22:20:44 +01:00
Zheng Bao a182cbdd62 cbfstool: Align the column of build hint message.
Change-Id: Ic217450411d7fa4e6c3a053be62d7c948dc7145e
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/2030
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-12-14 08:46:26 +01:00
Marc Jones 9915b37f10 coreinfo: Build libpayload from coreinfo makefile
Build libpayload and install it in the coreinfo directory.
Allows coreinfo to be built with a single make command.

Change-Id: I56982265555aae16e482b0a0040989c1f5317423
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/1995
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-12-13 10:37:28 +01:00
Dave Frodin 0b97f2978f libpayload: increase the default heap size
Coreinfo uses the default heap size and will blow up
if the USB keyboard is used.

Change-Id: I2ffae330ec34167b2ccfbd4c428e3e8306230f44
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/1980
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-12-13 08:26:12 +01:00
Dave Frodin 15a2c8f827 coreinfo: changes to get the USB keyboard working
A call to usb_initialize() was needed. Also needed to set several
curses flags. One to prevent keystrokes echoing to the display,
and one to allow extended keystrokes (like the KEY_F(n)) to be
seen when calling getch();

Change-Id: I495b42055a54603e4efb92b2845051434d88432d
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/1983
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-12-12 22:35:19 +01:00
Martin Roth e899e518d8 SB800: Add IMC ROM and fan control.
Add configuration for AMD's IMC ROM and fan registers for cimx/sb800
platforms.

- Allows user to add the IMC rom to the build and to configure the
  location of the "signature" between the allowed positions.
- Allows for no fan control, manual setup of SB800 Fan registers, or
  setup of the IMC fan configuration registers.
- Register configuration is done through devicetree.cb. No files need
  to be added for new platform configuration.
- Initial setup is for Persimmon, but may be extended to any cimx/sb800
  platform.

Change-Id: Ib06408d794988cbb29eed6adbeeadea8b2629bae
Signed-off-by: Martin Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/1977
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-12-12 22:35:03 +01:00
Martin Roth a17fd056d4 Rename generated hudson_romsig.bin for make clean
The file generated when the IMC or XHCI binaries are included in the rom
was named $(obj)/hudson_romsig.bin.  The problem with this is that it
doesn't get deleted when the user does a make clean.
changing the name to coreboot_hudson_romsig.bin makes this happen.

Change-Id: I19a40042fbf0f7b5633d7b35339c05ed90d3243b
Signed-off-by: Martin Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/1978
Tested-by: build bot (Jenkins)
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-12-12 22:34:46 +01:00