ANX7625 is used on Kingler board as the eDP bridge IC. Enable ANX7625
and configure display in mainboard_init() to support display in
firmware screen.
BUG=b:209930699
TEST=saw firmware display on eDP panel of kingler board.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ie8de5d8ba150d3ae086c7635601dbc0846aebe91
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Initialize and calibrate DRAM in romstage.
DRAM full calibration logs:
dram_init: dram init end (result: 1)
DRAM-K: Full calibration passed in 20014 msecs
TEST=DRAM full calibration pass.
BUG=b:202871018
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: I80a18a8be5b1d47a5f0f7afed9601c0884e69035
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Remove emi.h because emi.h is defined in common/include/soc.
Add dramc_param.h and dramc_soc.h to prepare for implementation of
DRAM full calibration.
TEST=build pass.
BUG=b:202871018
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: If8662ed43088ea5aa1fe6cb5b2c4bda2338c4387
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60385
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Previously (before CB:56965 [1]) mtk_dsi_send_init_command() would
ignore NULL initialization commands passed to it. However, in the
current code mipi_panel_parse_init_commands() doesn't check that (see
CB:57150 [2]), so we should check it on the caller side from
mtk_dsi_init().
[1] b2a1480191 device: Move MIPI panel library from
mainboard/google/kukui into common
[2] 4757a7ea33 mipi: Make panel init callback work directly on DSI
transaction types
BUG=b:202871018, b:209930699
TEST=emerge-corsola coreboot
BRANCH=none
Change-Id: I8196e3b135da273325e2e121523abb7fb230a49c
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
PS8640 is a low power MIPI-to-eDP video format converter.
VRF12 does not provide power to PS8640 on krabby.
In original patch, VRF12 is not used, and is set to hardware control
for low power. We change the setting to remove hardware control.
Therefore, if we want to control VRF12 by software, we can control
it directly.
BUG=b:210806060
TEST=build pass
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I87d6a94b6fb343590d563ac1554ff87b11c01549
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Add basic devapc (device access permission control) drivers.
DAPC driver is used to set up bus fabric security and data protection
among hardwares. DAPC driver groups the master hardwares into different
domains and gives secure and non-secure property. The slave hardware can
configure different access permissions for different domains via DAPC
driver.
1. Initialize devapc.
2. Set master domain and secure side band.
3. Set default permission.
BUG=b:202871018
TEST=build pass
Signed-off-by: Runyang Chen <runyang.chen@mediatek.corp-partner.google.com>
Change-Id: I5dad4f342eef3136c24c38259ad176dc86b7c0d7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
We use parts of SRAM_L2C as the memory of PRERAM_CBMEM_CONSOLE before
DRAM calibration. When we check cbmem, we found the content of this
memory is unreadable.
The L3 (can be used as SRAM_L2C) is 1MB in total. However the BootROM
has configured only half of L2/L3 cache as SRAM. Therefore, decrease
the size of each SRAM region to fit into the first half of the cache.
BUG=b:207725851
TEST=Bootblock log looked good in `cbmem -c`
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I6041767a1ac0a48ecdda29a0c35d90acf6ad0ef2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Current mainboard code supports different baseboard binding
example: brya uses BOARD_GOOGLE_BASEBOARD_BRYA and brask uses
BOARD_GOOGLE_BASEBOARD_BRASK Kconfig.
This patch makes the `BOARD_GOOGLE_BRYA_COMMON` Kconfig default
`n` and specific baseboard binding Kconfig can select this Kconfig.
It would also avoid adding if clause for specific baseboard binding
Kconfig everytime with introduction of newer mainboard in future.
TEST=Verified CONFIG_BOARD_GOOGLE_BRYA_COMMON=y while building brya
and brya coreboot.rom remains the same.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I754159447e68b8ac2ea21009cc801fc5ba5df56e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
This patch ensures ADL-P PCH can get selected by mainboard
variants to accommodate mainboards with ADL-N PCH in future.
TEST=Able to build and boot brya without any Kconfig change.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ifbcd1cd7f8ecafee22d50c3f3f20decc4cc62797
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60378
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The intel-spi driver maps the BIOS region of the flash as an mtd device
at /dev/mtdX. Since this system is intended for development purposes,
disable its write protection.
Change-Id: Ib73d14eb4e7df6e29433b8dfbeb77dbab4a85f08
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60375
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Config options and package names might change from channel to channel.
Thus, don't let nix-build depend on the locally configured NixOS
channel, but instead let `nixpkgs` point to a specific channel to ensure
that always a compatible channel is used.
For now, let `nixpkgs` point to NixOS 21.11, which is currently the
latest stable release. This needs to be updated after a new release.
Change-Id: Ia77c34f93f0e2c3d351ae229830adfce75a56ae4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Merge build scripts to `build.sh`. The new one takes the desired NixOS
config as an argument.
Example:
$ build.sh console.nix
Change-Id: I49360a5c57954a205c697a4ae07361779db2aa83
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60372
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There is a design issue of bit shift which will drop a bit for
USB3 phy on MT8195. Therefore, we add this patch to set USB phy
registers from value of efuse.
BUG=b:211528577
TEST=build pass
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Signed-off-by: Tianping Fang <tianping.fang@mediatek.corp-partner.google.com>
Tested-by: Tianping Fang <tianping.fang@mediatek.corp-partner.google.com>
Change-Id: I43cb6c1c795dd181d6eba7f3bc52e4eb1a602081
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60312
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Copied from commit df72b18d (mb/google/brya/var/taeko: Set vGPIO reset
type).Due to the vGPIO is not reset when we power on through S5, we
would met MCA when PCIE send L1 request without following Ack.
BUG=b:207070967
TEST=S0->S3->S5->power key->S3->S0, see if boot up normal
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: Id0df489fe5513c4975747d52c97cb3ee8e691782
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
It makes sense to provide limits.h via the types.h header.
Change-Id: I3ba189b998644c68068b85f25b11cff4d70c037d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55320
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Felix Singer