Running result.
superiotool r6131
Found Winbond W83527HG (id=0xb0, rev=0x73) at 0x2e
The documentation is not available yet.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6169 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
[PATCH] SB700 common FADT was not applied to this board because it was in the meanwhile added.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6167 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6166 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6165 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
broken them again. Instead rely on coreboot's dependencies to figure out
what to rebuild.
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6162 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
src/arch/x86.
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6161 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Factor out the ROM decode enable functionality into bootblock.c and
handle it via the usual TINY_BOOTBLOCK mechanism.
Use "select TINY_BOOTBLOCK" in the southbridge, not individual boards.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6159 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
All southbridges using TINY_BOOTBLOCK have a bootblock.c files which
simply includes an enable_rom.c files. As discussed on the mailing
list, drop the enable_rom.c file by merging it into bootblock.c.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6158 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The files debug.asl, globutil.asl, and statdef.asl are duplicated in
many K8/Fam10h boards. However, they're neither board-specific nor
K8/Fam10h-specific nor AMD-specific, so move them to src/arch/i386/acpi.
debug.asl contains generic chunks for I/O port 0x80 handling, and debug
output over serial port (init COM port, send byte, send string, etc).
globutil.asl contains utility methods for string comparison, string length
and similar stuff.
statdef.asl contains generic ACPI bit definitions / status codes from
the ACPI spec (not board- or chipset-specific).
This patch was mostly generated by:
mkdir src/arch/i386/acpi
svn add src/arch/i386/acpi
svn cp src/mainboard/amd/dbm690t/acpi/debug.asl src/arch/i386/acpi/
svn cp src/mainboard/amd/dbm690t/acpi/globutil.asl src/arch/i386/acpi/
svn cp src/mainboard/amd/dbm690t/acpi/statdef.asl src/arch/i386/acpi/
cd src/mainboard
find . -name debug.asl -exec svn rm {} \;
find . -name globutil.asl -exec svn rm {} \;
find . -name statdef.asl -exec svn rm {} \;
Abuild-tested.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6156 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
> Definitively a iasl problem, it can't even disassemble it's own
> output back to something equivalent to the input file.
> It seems to be generating Bytecode for the Add where it shouldn't.
Here is a solution using the SSDT.
Unfortunately iasl does not resolve simple arithmetic at compile
time, so we can not use Add(DEFAULT_PMBASE, PCNTRL) in the
Processor statement.
This patch instead dynamically generates the processor statement.
I can't use the speedstep generate_cpu_entries() directly since the
cpu doesn't support speedstep.
For now the code is in the southbridge directory, but maybe it
should go into cpu/intel/ somewhere.
IIRC notebook cpus of the era can already have speedstep, so it
would probably be possible to pair the i82371eb with a
speedstep-capable cpu...
Also, I don't know if multiprocessor boards (abit bp6?) would need
to be handled differently.
Abuild-tested.
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6153 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
DOTCONFIG make variable (defaults to .config).
Let abuild use that.
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6152 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
All K8/Fam10h boards use CAR, so move the "select CACHE_AS_RAM"
into the socket directories, and remove it from the individual boards.
Do the same for Intel CPUs/sockets where all boards use CAR.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6151 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
the prefix was introduced in the early v2 tree many years ago
because our old build system "newconfig" could not handle two files with
the same name in different paths like /path/to/usb.c and
/another/path/to/usb.c correctly. Only one of the files would end up
being compiled into the final image.
Since Kconfig (actually since shortly before we switched to Kconfig) we
don't suffer from that problem anymore. So we could drop the sb700_
prefix from all those filenames (or, the <componentname>_ prefix in general)
- makes it easier to fork off a new chipset
- makes it easier to diff against other chipsets
- storing redundant information in filenames seems wrong
Signed-off-by: <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6150 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
the prefix was introduced in the early v2 tree many years ago
because our old build system "newconfig" could not handle two files with
the same name in different paths like /path/to/usb.c and
/another/path/to/usb.c correctly. Only one of the files would end up
being compiled into the final image.
Since Kconfig (actually since shortly before we switched to Kconfig) we
don't suffer from that problem anymore. So we could drop the sb700_
prefix from all those filenames (or, the <componentname>_ prefix in general)
- makes it easier to fork off a new chipset
- makes it easier to diff against other chipsets
- storing redundant information in filenames seems wrong
Signed-off-by: <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6149 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Use w83627hf_set_clksel_48() where needed instead or open-coding the same
functionality, and also use w83627hf_enable_serial() instead of
w83627hf_enable_dev() (which does exactly the same, but isn't wrapped in the
enter/exit config mode functions).
Abuild-tested.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6143 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
De-asserts STRAP_BIF_all_valid for
PCIE-GFX core.
After lane reversal,
Asserts STRAP_BIF_all_valid for
PCIE-GFX core.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: QingPei Wang <wangqingpei@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6142 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
W83627DHG:
- Add proper "virtual LDN" handling for the LDNs that need it (i.e., those
that don't have their "enable" bit in bit 0 of the 0x30 register).
- Fix various I/O masks in the pnp_dev_info[] array as per
datasheet. Add missing PNP_IRQ0 to the W83627DHG_ACPI LDN.
W83627EHG:
- Similar to W83627DHG, improve the "virtual LDN" setup a bit (it was
mostly implemented already, though).
- Add missing PNP_IRQ0 to the W83627EHG_ACPI LDN.
Also: Fix up devicetree.cb of all boards using W83627DHG/W83627EHG to adapt
for the virtual LDNs.
include/device/pnp.h: Add comment that 'function' (which refers to the
LDN and should probably be renamed later) has to be at least 16 bits
wide. In theory LDNs could use u8, but due to the virtual LDN info being
encoded in the "high byte" of 'function' it must be at least u16.
asrock/939a785gmh/romstage.c: Drop unused GPIO6_DEV.
ibase/mb899/romstage.c: Use DUMMY_DEV instead of a specific LDN (serial
port 1 in this case) to avoid confusion. The global registers
manipulated there are accessible from any LDN.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6140 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6138 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Add libelf_cv_elf_h_works=no to produce a libelf.h for Cygwin.
Add GDB patch to handle #pragma pack in the i386-elf gcc target.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6137 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The read-modify-write wasn't needed. This is easier to understand.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6136 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6135 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Single channel (in slot DDR1 and DDR3) produces strange artefacts on screen (and hang)
Dual Channel (in DDR1 and DDR2 aka blue slot) - works nice
All slots populated - same case as Single channel - must be something wrong with UMA.
Tested with 2x 512MB CAS 2.5 DDR400
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6134 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
> Stefan Reinauer wrote:
> > The specified IO port is most likely wrong. As the comment mentions, the
> > SSDT is a good place for that. A preprocessor define used both in the
> > CPU init code and in the asl would solve the problem without an SSDT.
> > For some info on CPU SSDT creation on intel check out
> > src/cpu/intel/speedstep/acpi.c
>
> The IO port is ok (and I wrote the comment myself ;)):
> DEFAULT_PMBASE is 0xe400
> PCNTRL reg offset is 0x10
>
> Using the preprocessor will probably work too if iasl can do simple
> arithmetic (likely yes), I'll look into that.
BTW, my first idea was to use an acpi method that looks up pmbase in
the pci cfg space, but when I define a method like this:
Method(TEST, 2)
{
Return (Add(Arg0, Arg1))
}
I get:
|build/mainboard/asus/p2b/dsdt.ramstage.asl 9: Processor (CPU0,
|0x01, TEST(0xe400, 0x10), 0x06) {}
|Error 4096 - syntax error, unexpected PARSEOP_NAMESEG,
|expecting ')' ^
While using the builtin Add() directly works.
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6132 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The patch was tested by a user on IRC who had the F71889FG. I
wrote it using documentation from Fintek's website available here:
http://www.fintek.com.tw/files/productfiles/F71889_V0.28P.pdf
This patch also seems to work for the F71889ED, which uses 0x09 and 0x09 for
chip ID bytes 1 & 2. However, I have not been able to find documentation to
verify that the two chips are identical from superiotool's perspective.
Signed-off-by: David Hendricks <dhendrix@google.com>
Signed-off-by: Alec Ari <neotheuser@ymail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6131 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- pmbase is on southbridge function 3 on I82371XX
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6128 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
I cleaned up the patch and moved most of the dsdt.dsl and
acpi_tables.c into the southbrige/northbridge directory.
Updated patch should fix abuild error and incorporates suggestions
on irc by uwe (thanks for the comments).
Thanks to Idwer Vollering <vidwer@gmail.com> for the original patch.
Tested:
Linux (poweroff, powerbutton event)
XP (poweroff, powerbutton event)
Abuild-tested
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6127 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
In bcm5785_enable_rom(): Use PCI IDs from pci_ids.h instead of hardcoding,
and use 'dev' instead of 'addr' as device_t variable name.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6126 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6125 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Also, add missing license header to amd8111_enable_rom.c, add some more code
comments and use PCI IDs from pci_ids.h instead of hardcoding.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6124 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Also, move CONFIG_HT_CHAIN_END_UNITID_BASE #ifdef block to mcp55.h to make
the build work (but this is a good idea anyway, as it's used in
multiple files).
Abuild-tested.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6123 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This adds the board-specific parts for S3 support on the M2V board.
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6122 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
initialized properly because the pcie link takes some time to come
up.
I set the timeout rather arbitrary to 100ms, this is what a BIOS_ERR
and higher only boot looks like on my system (with pcie printks set
to BIOS_ERR so they show up):
|Device error
|Device error
|PCI: 00:02.0 PCIe link up after 35800 us
|PCI: 00:03.0 PCIe link up after 12900 us
|PCI: 00:03.1 PCIe link timeout
|PCI: 00:03.2 PCIe link up after 32000 us
|APIC: 00 missing read_resources
|I2C: 01:50 missing read_resources
|I2C: 01:51 missing read_resources
|I2C: 01:52 missing read_resources
|I2C: 01:53 missing read_resources
|Start bios (version pre-0.6.2-20101025_023503-nukunuku)
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6121 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
AMD RS780 uma graphics. Tested with frame buffer sizes 64m through 1GB
by running dxdiag and Windows media player at 1600x1200 true color.
Additional changes needed to boot Win7 on Mahogany_fam10 will follow.
-- Enable and program the debug bar as required by the ATI graphics driver.
First, make the debug bar writable and allow resource allocation code
to program it. Once programmed, enable its operation.
-- Disable the family 10h processor mmconf while the RS780 mmconf is in use.
-- Make strap programming more closely follow the reference BIOS.
-- Disable PCIe bar 3 after using it.
-- UMA size is no longer hardcoded.
-- Disable write combining for all steppings to eliminate stability problem.
-- Correct task file data.
-- Improve the accuracy of the Atom table that passes information to the driver.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6120 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Zheng Bao