Commit graph

2223 commits

Author SHA1 Message Date
Ricardo Quesada
2e0b5c4007 elog: Define constant for RW region name
This CL indroduces the ELOG_RW_REGION_NAME. This constant replaced the
hardcoded "RW_ELOG" value. This constant will be used also by elogtool
(see CL in the commit chain).

BUG=b:172210863

Change-Id: Ie8d31204e65fd67d52b0f8ced7b8c1ffdcf5b539
Signed-off-by: Ricardo Quesada <ricardoq@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56986
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-26 18:50:56 +00:00
Ricardo Quesada
e929a75fbe elog: move functionality to commonlib/bsd
This commit moves some drivers/elog/ functionality to commonlib/bsd
since they will be called from util/cbfstool/.

In particular:
 * elog_fill_timestamp(), elog_update_checksum(), elog_checksum_event()
   were moved to commonlib/bsd/elog
 * elog_fill_timestamp() receives the time parameters and updates the
   event based on the "time" arguments.

The original elog_*() functions were written by Duncan Laurie
(see CB:1311) and he gave permission to re-license the code to BSD.

BUG=b:172210863

Change-Id: I67d5ad6e7c4d486b3d4ebb25be77998173cee5a9
Signed-off-by: Ricardo Quesada <ricardoq@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-26 18:50:29 +00:00
Felix Held
42df9af4c4 drivers/intel/fsp2_0: rename soc_validate_fsp_version
Rename soc_validate_fsp_version to soc_validate_fspm_header, since it
can not only be used to check the version info in the FSP-M binary's
header, but also to check every other field in the binary's header. This
is a preparation for a follow-up patch that implements this function to
check the FSP-M binary's size.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ifadcfd1869bea0774dc17b69c5d1e1c241a45de1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-26 15:19:06 +00:00
Julius Werner
5ff1808f20 device/mipi: Move to drivers/mipi
Sounds like we prefer to have this under drivers/ instead of device/.
Also move all MIPI-related headers out from device/ into their own
directory.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ib3e66954b8f0cf85b28d8d186b09d7846707559d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-08-26 15:18:45 +00:00
Ricardo Quesada
954df3d6bf include/bcd: move bcd code to commonlib/bsd/include
Move bcd2bin() / bin2bcd() functions to commonlib/bsd/include/

Also, the license is changed from GPL to BSD.
This is because it is needed from "utils" (see CL in the chain).

For reference bin2bcd() & bcd2bin() are very simple functions.
There are already BSD implementations, like these ones (just to
name a few):
https://chromium.googlesource.com/chromiumos/platform/mosys/+/refs/heads/main/include/lib/math.h#67
http://web.mit.edu/freebsd/head/sys/contrib/octeon-sdk/cvmx-cn3010-evb-hs5.c

BUG=b:172210863
TEST=make (everything compiled Ok).

Change-Id: If2eba82da35838799bcbcf38303de6bd53f7eb72
Signed-off-by: Ricardo Quesada <ricardoq@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56904
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-23 14:08:47 +00:00
Jeremy Soller
191a8d7d2e soc/intel/common: Add TGL-H PCI IDs
Add TGL-H PCI IDs from the Processor and PCH EDS docs.

Reference:
- Intel doc 615985
- Intel doc 575683

Change-Id: I751d0d59aff9e93e2aa92546db78775bd1e6ef22
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-19 13:51:59 +00:00
Eric Lai
b6f6e01bcb drivers/generic/alc1015: Add HID to support alc1019
ALC1019 will use the ACPI compatible and share the same driver with
ALC1015. Add HID to support more compatible ICs.

BUG=b:195891240
TEST=ALC1019P driver can probe properly.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I3e98297f3a39048b24d61e61ca95c60cd2037eb5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-12 17:57:55 +00:00
Tim Wawrzynczak
29f3a88d9f drivers/uart/acpi: Update _S0W return value to D3hot
In order to support wake from D3cold, most devices require extra
circuitry and possibly out-of-band communications to the host.
Therefore, assume that most UARTs that do have wake capabilities support
wake from D3hot rather than D3cold.

BUG=b:187228954
TEST=compile

Change-Id: I24d6d0e81d980fc9c910d8f47f557c88990b6400
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-09 15:03:36 +00:00
Tim Wawrzynczak
04c71deceb drivers/spi/acpi: Update _S0W return value to D3hot
In order to support wake from D3cold, most devices require extra
circuitry and possibly out-of-band communications to the host.
Therefore, assume that most SPI peripherals that do have wake
capabilities support wake from D3hot rather than D3cold.

This also allows coreboot to expose a power resource to perform power
sequencing for a SPI peripheral that is intended to retain power in
S3/S0ix.

If support for a device with d3cold wake support is needed, it could be
added in later as an option.

BUG=b:187228954
TEST=compile

Change-Id: I1d739b49c1a43007eb0199fe39b3b7d7375e6577
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-09 15:03:21 +00:00
Tim Wawrzynczak
72c0b54efb drivers/i2c/da7219: Update _S0W to D3hot
The DA7219 does not support wake from D3cold, therefore update the
return value of _S0W from D3cold to D3hot.

BUG=b:187228954
TEST=compile

Change-Id: If03f83bb00ec90a2a6646d2c99d8bcc7e5533ac2
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-09 15:03:14 +00:00
Ricardo Quesada
d45e70c124 Move elog_internal.h to commonlib/bsd/include
Move elog_internal.h to commonlib/bsd/include/bsd/.
And rename it from elog_internal.h to elog.h.

Since this file will be included from util/ it also converts the "uNN"
types into "uintNN_t" types.

The two defines that are not used by util/ are moved to
drivers/elog/elog.c, the only file that includes them.

Move also the function elog_verify_header() from drivers/elog/, to
commonlib/bsd/elog.c since this function will be called from util/
as well.

The rationale behind moving elog's defines & structs to
commonlib/bsd/include is to make them available to util/ tools and/or
payloads (should it be needed in the future).

The files that are being relicensed to BSD were coded by Duncan Laurie,
and he is Ok with the relicense.

BUG=b:172210863

Signed-off-by: Ricardo Quesada <ricardoq@google.com>
Change-Id: Ia1aefea705ddd417a1d9e978bb18ab6d9a60cad6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-04 15:15:55 +00:00
Nikolai Vyssotski
3c3d2cf77f src/drivers/intel/fsp2_0: allow larger FSP 2.0 header
This is in preparation for migrating EDK2 to more recent version(s). In
EDK2 repo commit f2cdb268ef appended an additional field to FSP 2.0
header (FspMultiPhaseSiInitEntryOffset). This increases the length of
the header from 72 to 76. Instead of checking for exact length check
reported header length against known minimum length for a given FSP
version.

BUG=b:180186886
TEST=build/boot with both header flavors
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Change-Id: Ie8422447b2cff0a6c536e13014905ffa15c70586
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56190
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-24 15:18:43 +00:00
Werner Zeh
35e1fca8f2 drivers/intel/i210: Set PCI bus master bit only if allowed
Set the bus master bit only if the global Kconfig switch
PCI_ALLOW_BUS_MASTER_ANY_DEVICE is enabled. For now the bus master bit
is needed for i210 because of some old OS drivers that do not set it
and won't work properly without it.

Change-Id: I6f727e7f513f4320740fbf49e741cea86edb3247
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-07-23 13:18:14 +00:00
Nico Huber
dee281d03f drivers/pc80/rtc: Make use of alt-century byte configurable
This legacy alt-century byte sits amidst CMOS and conflicts many option
tables. It usually has no meaning to the hardware and needs to be main-
tained manually. Let's disable its usage by default if the CMOS option
table is enabled.

Change-Id: Ifba3d77120c2474393ac5e64faac1baeeb58c893
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-07-23 11:05:30 +00:00
Shaik Sajida Bhanu
7ce0236941 drivers/spi: Increase sector number to 14 for Winbond W25Q512NW-IM
Update proper number of sectors info for winbond W25Q512NW-IM chip

BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board

Change-Id: I12a22321bb9180e32cd47faa6ac3960ba5b2dfb8
Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56038
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-22 17:21:29 +00:00
Meera Ravindranath
1b8159b3a1 drivers/intel/gma: Support IGD Opregion 2.1
List of changes:
1. Define new configs for Opregion versions.
2. Assign RVDA to relative address of the Opregion buffer
   in case of opregion 2.1+.

BUG=b:190019970
BRANCH=None

Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I95a9f3df185002a4e38faa910f867ace0b97ac2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-17 13:48:00 +00:00
Julius Werner
df5062215f drivers: spi_flash: Add Fast Read Dual I/O support
The Fast Read Dual Output and Fast Read Dual I/O commands are
practically identical, the only difference being how the read address is
transferred (saving a whooping 2 bytes which is totally irrelevant for
the amounts of data coreboot tends to read). We originally implemented
Fast Read Dual Output since it's the older command and some older
Winbond chips only supported that one... but it seems that some older
Macronix parts for whatever reason chose to only support Fast Read Dual
I/O instead. So in order to make this work for as many parts as
possible, I guess we'll have to implement both. (Also, the Macronix
device ID situation is utter madness with different chips with different
capabilities often having the same ID, so we basically have to make a
best-effort guess to strike a trade-off between fast speeds and best
chance at supporting all chips. If this turns out to be a problem later,
we may have to add Kconfig overrides for this or resort to SFDP parsing,
although that would defeat the whole point of trying to be fast.)

BUG=b:193486682
TEST=Booted CoachZ (with Dual I/O)

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ia1a20581f251615127f132eadea367b7b66c4709
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-07-15 14:05:34 +00:00
Meera Ravindranath
92637df79a drivers/intel/gma: Restructure Opregion version info code
Define a structure for opregion version information to align
with spec/kernel.

BUG=b:190019970
BRANCH=None

Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I93a9f2df186002a4e38caa910f867bce0b97ac2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-15 14:04:11 +00:00
Angel Pons
dd405bc018 drivers/usb/acpi: Avoid dereferencing maybe-NULL pointer
Do not dereference a pointer before checking whether it is NULL.

Change-Id: Icbe9ae99d91fd587d8e56cf3a0dcb59834ee6d07
Found-by: Coverity CID 1458232
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56266
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14 21:26:47 +00:00
Angel Pons
afab34c372 drivers/usb/acpi: Replace unneeded memcpy use
A regular assignment works just as well and also allows type-checking.
It also avoids a common mistake where `sizeof` is applied to a pointer
to obtain the size of the data it points to, without dereferencing it.

Found-by: Coverity CID 1458231
Change-Id: I7ed05322c3c911f3da4145f81e4d9760a275fec2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56265
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14 21:26:34 +00:00
Arthur Heymans
78ab06ace9 src: Use initial_lapicid() instead of open coding it
Since initial_lapicid() returns an unsigned int, change the type of the
local variables the return value gets assigned to to unsigned int as
well if applicable. Also change the printk format strings for printing
the variable's contents to %u where it was %d before.

Change-Id: I289015b81b2a9d915c4cab9b0544fc19b85df7a3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55063
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14 02:19:28 +00:00
Felix Held
46e6a5883e Revert "drivers/intel/fsp2_0: use FSP to allocate APEI BERT memory region"
This reverts commit ce0e2a0140 which was
originally introduced as a workaround for the bug that the Linux kernel
doesn't know what to do with type 16 memory region in the e820 table
where CBMEM resides and disallowed accessing it. After depthcharge was
patched to mark the type 16 region as a normal reserved region, the
Linux kernel now can access the BERT region and print BERT errors. When
SeaBIOS was used as payload it already marked the memory region
correctly, so it already worked in that case.

After commit 8c3a8df102 that removed the
usage of the BERT memory region reserved by the FSP driver by the AMD
Picasso and Cezanne SoCs and made them use CBMEM for the BERT region,
no other SoC code uses this functionality. The Intel Alderlake and
Tigerlake SoCs put the BERT region in CBMEM and never used this reserved
memory region and the change for the Intel server CPU to use this was
abandoned and never landed in upstream coreboot. AMD Stoneyridge is the
only other SoC/chipset that selects ACPI_BERT, but since it doesn't
select or use the FSP driver, it also won't be affected by this change.

TEST=Behavior of the BERT code doesn't change on Mandolin

Change-Id: I6ca095ca327cbf925edb59b89fff42ff9f96de5d
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56163
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-12 17:34:00 +00:00
Maulik V Vaghela
9c7122f1e8 drivers/intel/usb4/retimer: remove redundant structure member group(PLD)
Currently, we get PLD information from USB port structure itself, so
devicetree does not need to fill PLD structure anymore. Thus remove
obsolete variable.

Change-Id: I7a561677ab65ddb870d1b00b35ee9d7a22ef9c70
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-12 07:29:48 +00:00
Maulik V Vaghela
0f7e086229 drivers/intel/usb4/retimer: Update code to assign correct port number
Since TBT controller can have maximum 2 ports per controller, our
code will loop over DFP structure twice and determine port number.

Retimer driver used to assign port number as below:
1. Check if power GPIO is assigned for particular DFP entry or not
2. If entry is there, assign loop count as port number

Since loop count is 2, retimer will never assign port number = 2
even if it's present. In case of more than 1 controller, port number
assigned will still be 0 or 1 even though actual port index might
be 2 or 3. This will create an issue where even if you do transaction
on device on controller 2 (port index 2 or 3), EC will route it on
port 0 or 1 due to incorrect port index.

Update the driver flow as per below to handle this scenario:
1. Check if power GPIO is assigned for particular DFP entry or not
2. Get USB port number from config since it's stored in usb port
   information under devicetree
3. Pass the port number to ACPI SSDT and EC code

Above changes will ensure that we're assigning correct port
number as per calculation and EC will use correct port index.

BUG=b:189476816
BRANCH=None
TEST=Checked that retimer firmware update works on both ports and update
happens on correct port index.

Change-Id: Ib11637ae39046e0afdacd33bc34e8a59e6f2bfb1
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-12 07:29:32 +00:00
Maulik V Vaghela
8e885a57b1 drivers/usb/acpi: Create function to get PLD information
Create a separate function to get PLD information from USB device.
This is helpful in retimer driver where we can attach same USB
port information to retimer instance and we can avoid duplication
of information.

BUG=None
BRANCH=None
TEST=Check if code compiles and function returns correct value

Change-Id: Iaaf140ce1965dce3a812aa2701ce0e29b34ab3e7
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-12 07:29:24 +00:00
Sumeet Pawnikar
f96aa7a687 IMOK: Add IMOK method support for DPTF
Add IMOK method support for DPTF

BRANCH=None
BUG=b:187797417
TEST=Built and tested on dedede board

Change-Id: I8edfa3bcaa6bde0b9690fcace000cd582dcc81d2
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-08 15:47:25 +00:00
Raul E Rangel
43e993b3b0 drivers/intel/fsp2: Change FSPS returned message to INFO
This message is not an error, but just informational.

BUG=none
TEST=Boot with CONSOLE_LOGLEVEL_3 and no longer see it printed

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ifb64edbe029cafa82aec99aa50de47f51cd50dce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55971
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-02 23:12:54 +00:00
Maulik V Vaghela
a6b60ebedb drivers/intel/gma: Move extended VBT just below opregion
Currently the flow for opregion init is as below:
1. Allocate memory for opregion first (cbmem_add(opregion))
2. Check if VBT size > 6 KiB (this requires extended VBT support)
3. In case of extended VBT requirement, we allocate another chunk
   of memory which is equal to size of VBT (cbmem_add(extended_vbt))
4. Pass physical address pointer to OS via RVDA

We can optimize the above flow to allocate single chunk of memory by
checking VBT size in earlier step. The new optimized flow for opregion
init is as below:
1. Check if VBT size > 6 KiB (this requires extended VBT support)
2. In case of extended VBT requirement, total memory to be allocated
   is calculated as sizeof(opregion) + sizeof (extended_vbt)
   In case where VBT size is < 6 KiB, total memory requirement would
   be equal to sizeof(opregion)
3. Based on above calculation, allocate single chunk of memory based on
   total size.

This will also be helpful for the case of virtualization where guest
users don't have access to physical address and when it needs relative
address of VBT compared to absolute address.

In case of opregion 2.1 spec, we need to pass relative address of
VBT from opregion base in RVDA. This optimization will help in meeting
this requirement since relative address of extended VBT is easy to get.
This change will ensure that it meets opregion specification
requirement and will be compatible with future versions as well.

BUG=b:190019970
BRANCH=None
TEST=check the address of extended VBT region and address is coming
correctly.

Change-Id: Ic0e255df63145409096b0b9312c6c51c05f49931
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-01 16:36:47 +00:00
Sumeet R Pawnikar
3657187789 drivers/intel/dptf: Add OEM variables support
This adds OEM variables feature under DPTF as per BWG doc #541817. Using
this, platform vendors can expose an array of OEM-specific values as OEM
variables to be used in determining DPTF policy. These are obtained via
the ODVP method, and then simply exposed under sysfs. In addition, these
gets updated when a notification is received or when the DPTF policy is
changed by userspace.

BRANCH=None
BUG=b:187253038
TEST=Built and tested on dedede board

Change-Id: Iaf3cf7b40e9a441b41d0c659d76895a58669c2fb
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-01 12:12:33 +00:00
Angel Pons
b554b7c51f SMBIOS: Drop now-unnecessary unions
Now that the refactoring is complete, the unions for the table header
are no longer needed. Therefore, drop them.

Change-Id: I4e170e84a12646386d3fd84ae973dd6c18f25809
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-01 07:38:32 +00:00
Angel Pons
a37701afa3 SMBIOS: Introduce smbios_full_table_len function
Introduce the `smbios_full_table_len` function to consolidate table
length calculation. The case where the length of a table equals the
length of the structure happens when a table has no strings.

Change-Id: Ibc60075e82eb66b5d0b7132b16da000b153413f9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-07-01 07:38:00 +00:00
Angel Pons
d62a5012d6 SMBIOS: Introduce smbios_carve_table function
Factor out some boilerplate code into a helper `smbios_carve_table`
function, which zeroes out the table memory and fills in the header
fields common to all tables.

Change-Id: Iece2f64f9151d3c79813f6264dfb3a92d98c2035
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-07-01 07:37:21 +00:00
Angel Pons
ca01baa065 SMBIOS: Introduce struct for SMBIOS table header
All SMBIOS `type X` tables start with the same 4-byte header. Add a
struct definition for it, and use it where applicable. The union is
temporary and allows doing the necessary changes in smaller commits.

Change-Id: Ibd9a80010f83fd7ebefc014b981d430f5723808c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-01 07:37:04 +00:00
Angel Pons
35b99c64e6 SMBIOS: Avoid sizeof on struct type
Where applicable, use the size of the associated variable.

Change-Id: Ibbac2a82893232a6f87182a6a965b84a599d633e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-07-01 07:35:02 +00:00
Angel Pons
808692b4f4 drivers/mrc_cache: Avoid sizeof on struct type
Where applicable, use the size of the associated variable.

Change-Id: Icf4f1c8fe9f54c44b041a65eb46d6ec9f9fd6367
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-01 07:26:33 +00:00
Varshit B Pandya
6a103907f1 drivers/intel/mipi_camera: Change type for gpio_num to uint16_t
gpio_num is used to indicate the GPIO which is taken from gpio_soc_defs.h file.
Support for dynamic generation of ASL file for Camera was added for JSL
when there were less than 256 GPIOs. ADL now has more GPIOs and therefore
uint8_t is not enough any more

Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I0a5fdb612c8cf689d356af8591b9ad101360c25d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55538
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-21 05:34:58 +00:00
Lean Sheng Tan
fefc2ea4c4 intel/fsp2_0: Add FSP_ARRAY_LOAD macro
Add FSP_ARRAY_LOAD macro for checking and loading
array type configs into array type UPDs to increase readability.

Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I307340a2bfc0a54f2ab7241af2f24dfbf8bb111d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55559
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-18 06:03:16 +00:00
Angel Pons
33dddc46d0 drivers/intel/gma/opregion.c: Re-add lost log message
Commit 926949d64c (drivers/intel/gma:
Restructure IGD opregion init code) accidentally dropped this print
statement. As it can be useful for debugging purposes, add it back.

Change-Id: Iebd9e02bccc77538c0eed1e549294408586322f2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55567
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.corp-partner.google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-18 04:42:02 +00:00
Sugnan Prabhu S
9418e33aef drivers/intel/mipi_camera: Remove unnecessary __packed attribute
This patch removes unnecessary __packed attribute from the structure
defined in chip.h

BUG=None
TEST=Tested WFC camera on Brya

Change-Id: I1174606cd22cd353f01d865d0c25bb6f8f8de055
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55566
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-18 04:35:47 +00:00
Kyösti Mälkki
8c9a89de99 arch/x86/ioapic: Drop irq_on_fsb as a configurable item
APIC Serial Bus pins were removed with ICH5 already, so a choice
'irq_on_fsb = 0' would not take effect. The related register BOOT_CONFIG
0x3 is also not documented since ICH5.

For emulation/qemu-q35 with ICH9 the choice INTERRUPT_ON_APIC_BUS was
wrong and ignored as BOOT_CONFIG register emulation was never implemented.

For ICH4 and earlier, the choice to use FSB can be made based on the
installed CPU model but this is now just hardwired to match P4 CPUs of
aopen/dxplplusu.

For sb/intel/i82371eb register BOOT_CONFIG 0x3 is also not defined
and the only possible operation mode there is APIC Serial Bus, which
requires no configuration.

Change-Id: Id433e0e67cb83b44a3041250481f307b2ed1ad18
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55257
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-16 19:54:49 +00:00
MAULIK V VAGHELA
926949d64c drivers/intel/gma: Restructure IGD opregion init code
Restructuring opregion VBT related code to make it more generalize
for future revision of opregion spec.

Moved logic to locate VBT from different region (CBMEM, PCI option
ROM or VBIOS) into separate function.

Created a new function to check if extended VBT region is required.
This will be helpful in the subsequent changes to determine if
extended VBT region is needed and handle memory allocation
accordingly.

BUG=None
BRANCH=None
TEST=check the address of extended VBT region and address is coming
correctly.

Change-Id: I479d57cd326567192a3cd1969f8125ffe1934399
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-06-11 07:38:13 +00:00
Shaik Sajida Bhanu
5ef1a839c7 drivers/spi: Add winbond chip details
Added winbond W25Q512NW chip details.

Change-Id: I5545c9431891f7fa74c1527591fb7c3cd3aba687
Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55375
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2021-06-11 07:33:33 +00:00
Martin Roth
146508d749 drivers/intel/fsp2_0: Add timestamps for loading FSPM & FSPS
The loads of the FSPM and FSPS binaries are not insignificant amounts of
time, and without these timestamps, it's not clear what's going on in
those time blocks.  For FSPM, the timestamps can run together to make it
look like that time is still part of the romstage init time.

Example:
   6:end of verified boot                              387,390 (5,402)
  13:starting to load romstage                         401,931 (14,541)
  14:finished loading romstage                         420,560 (18,629)
 970:loading FSP-M                                     450,698 (30,138)
  15:starting LZMA decompress (ignore for x86)         464,173 (13,475)
  16:finished LZMA decompress (ignore for x86)         517,860 (53,687)
...
   9:finished loading ramstage                         737,191 (18,377)
  10:start of ramstage                                 757,584 (20,393)
  30:device enumeration                                790,382 (32,798)
 971:loading FSP-S                                     840,186 (49,804)
  15:starting LZMA decompress (ignore for x86)         853,834 (13,648)
  16:finished LZMA decompress (ignore for x86)         888,830 (34,996)

BUG=b:188981986
TEST=Build & Boot guybrush, look at timestamps.

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I5796d4cdd512799c2eafee45a8ef561de5258b91
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-10 20:47:59 +00:00
Kyösti Mälkki
8cc25d229f drivers/generic/ioapic: Use arch/x86/ioapic
Change-Id: Ibfaf6693288005463e45831fe100a5052e97cf2f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55185
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-07 21:01:56 +00:00
Raul E Rangel
6b4b4a8349 drivers/pcie/rtd3/device: Add PCIe RTD3 driver
This driver was inspired from soc/intel/common/block/pci/rtd3. I decided
to copy and modify it because the Intel driver has a lot of Intel
specific code.

This driver has been stripped down to only provide a power resource and
set the StorageD3Enable property. This driver is SoC agnostic and does
not handle suspending the actual PCIe root port. That should be
implemented by an SoC specific driver.

This is required for Guybrush to suspend/resume properly because the
NVMe power is tied to the S0 power rails, so the kernel needs to place
the device into D3.

BUG=b:184617186
TEST=Guybrush is able to suspend/resume properly. Also see power
resource get enabled / disabled.
[   56.075559]     power-0416 __acpi_power_off      : Power resource [RTD3] turned off
[   56.075562] device_pm-0279 device_set_power      : Device [PXSX] transitioned to D3cold
[   56.075567] pci_pm_suspend_noirq: nvme 0000:02:00.0: PCI PM: Suspend power state: D3cold
[   56.075569] nvme 0000:02:00.0: pci_pm_suspend_noirq+0x0/0x413 returned 0 after 15978 usecs

[  123.464874] nvme 0000:02:00.0: calling pci_pm_resume_noirq+0x0/0x11d @ 7, parent: 0000:00:02.4
[  123.464891] acpi_device_set_power: ACPI: \_SB_.PCI0.GP14.PXSX: Power state change: D3cold -> D0
[  123.464982]     power-0360 __acpi_power_on       : Power resource [RTD3] turned on
[  123.464984] device_pm-0279 device_set_power      : Device [PXSX] transitioned to D0
[  123.465039] nvme 0000:02:00.0: pci_pm_resume_noirq+0x0/0x11d returned 0 after 158 usecs

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I2adfc925183ff7a19ab97e89212bc87c40d552d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-07 11:35:47 +00:00
Matt DeVillier
7ca3ecb73a drivers/smmstore: Enable SMMSTORE V2 by default for Tianocore UEFIPAYLOAD
Tianocore UEFIPAYLOAD now supports SMMSTORE V2, so enable it by default

Change-Id: I33582427fe9d3fc7c15014d3a04fcdc533cb1ac8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-07 05:06:23 +00:00
Werner Zeh
1e02ad3f5a drivers/i2c/designware: Report I2C timings for additional bus speeds
Since the OS provides its own driver for the I2C controller it can
choose to use a bus speed other than the one used at coreboot runtime.
In this case it would be good to provide a way how the needed bus
timings are communicated to the OS, since these are very board-specific
and there is no way that the OS can know them other than read the
appropriate ACPI reported timings.
This patch adds some code to report additional bus speed timings if
there are some defined in the devicetree.

Change-Id: If921e0613864660dc1bb8d7c1b30fb9db8ac655d
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-06-04 12:39:06 +00:00
Deepti Deshatty
c146daf8a3 intel/common/block: Move mainboard api to tcss common block
As per the comments in CB:54090  mainboard api
mainboard_tcss_get_port_info() is simplified and moved to tcss common
block code.

Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.com>
Change-Id: I7894363df4862f7cfe733d93e6160677fb8a9e31
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-06-04 12:36:07 +00:00
Varshit B Pandya
4113bc07ed drivers/intel/mipi_camera: Add macros to increase code readability
This will be used to pass information to driver through ACPI in devicetree.
Example https://review.coreboot.org/c/coreboot/+/52013

register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3"
register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ"

TEST=Add these macros in devicetree, build and check static.c for consistency

Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.corp-partner.google.com>
Change-Id: Ia4137e09c934bf06857ceedb933e616bed5070dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55097
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-01 21:36:59 +00:00
Werner Zeh
686018988c drivers/pc80/mc146818rtc: Check date and time for sanity
There are cases where the RTC_VRT bit in register D stays set after a
power failure while the real date and time registers can contain rubbish
values (can happen when RTC is not buffered). If we do not detect this
invalid date and/or time here and keep it, Linux will use these bad
values for the initial timekeeper init. This in turn can lead to dates
before 1970 in user land which can break a lot assumptions.

To fix this, check date and time sanity when the RTC is initialized and
reset the values if needed.

Change-Id: I5bc600c78bab50c70372600347f63156df127012
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54914
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-30 20:28:14 +00:00