By using mp_run_on_all_cpus_synchronously to run APs MTRR init, it
gurantees the BSP will run post_cpus_add_romcache until all APs finishes
_x86_setup_mtrrs task.
BUG=b:225766934
TEST=Test on redrix and found the MTRR race condition on AP/BSP is gone.
Change-Id: I1fd889f880a0c605e6c739423a434d2adbc12d26
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
MTRR is a core level register which means 2 threads in one core share
same MTRR. There is a race condition could happen that AP overrides
BSP MTRR unintentionally.
In order to prevent such race condition between BSP and APs, this
patch provides a function to let BSP assign tasks to all APs and wait
them to complete the assigned tasks.
BUG=b:225766934
Change-Id: I8d1d49bca410c821a3ad0347548afc42eb860594
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63566
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change matches what we already do for cezanne. It will allow the
GPIO controller to work correctly in windows.
BUG=b:175146875
TEST=Boot windows and verify GPIO controller binds correctly and touch
screen works. Also boot linux and verify touchpad still works.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I998e286de18d3e3f8b2fe610d17aef94a6cf5477
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Specify the USB PHY settings in the devicetree instead of relying on the
FSP defaults. The USB PHY configuration for Chausie are taken from the
internal UEFI code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8cc38e6e26d53802773fe3c405415de15cca98a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
With this patch, the ThinkLight on the ThinkPad T60 can be controlled
through the OS. This was initially done for the X201 in f63fbdb6:
mb/lenovo/x201: Add support for ThinkLight.
After applying this patch, the light can be controlled like this:
echo on >/proc/acpi/ibm/light
echo off >/proc/acpi/ibm/light
Or through sysfs at /sys/class/leds/tpacpi::thinklight
Change-Id: I47f878533d36857d002d2e2605cc8bc7e1d960c9
Signed-off-by: Stefan Ott <stefan@ott.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Demote log level from error to notice. People should aware the SPD
decode might be wrong if it's not the support type.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I55f0968b78baaa2fc9a6bbebf6712fb8bfd349f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Clang does not like array declarations inside plain switch cases. There
are 2 options to fix this: use a block inside the switch statement, or
declare it outside the switch statement. This does the latter.
Change-Id: I9a02136fd63ac171b2bec4647c30c7eece930246
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
The bootblock is loaded from IFWI so there is no need to have it in
cbfs.
Also remove the FIT handling as that is also handled by the IFWI.
TESTED: up/squared still boots
Change-Id: I8e70e080765dd7306074a8cf71c8795b8fbbb8a2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63225
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Floats are not allowed in coreboot.
As the compiler rounded down the value, do so in the code too as this
is a known good value.
Change-Id: I4e180d4cb8e0e1aa68186bfc1daffdc5c339dc64
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
CID 1488814: Uninitialized variables (UNINIT)
Commit c66ea98 introduced an issue after static analysis on merge.
Because every APIC is associated with a CPU, this did not result in
any issues at runtime but should be fixed/cleaned up. Now, the path
name is initialized to null.
Fixes: Coverity CID 1488814, commit c66ea98
TEST=Built on brya
Change-Id: I0cfc8fd7a0c39e6610a9361630e3755293084f3d
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Amdfwtool creates AMD firmware images however there is currently no way
to get information from an existing image. This commit adds amdfwread to
support that functionality. At the moment only reading PSP soft fuse
flags is supported. Example usage: `amdfwread --soft-fuse bios.bin`,
example output: `Soft-fuse:0x400000030000041`.
BUG=b:202397678
TEST=Ran amdfwread and verified that it correctly reads the soft fuse
bits, verified that built AMD FW still boots on DUT
Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: I15fa07c9cad8e4640e9c40e5539b0dab44424850
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Clang has a limit for the number of nested brackets in CPP.
For soc/intel/common/block/include/intelblocks this is a problem as it
largely exceeds the default limit of 256.
Change-Id: I93038f918e07f735394fc495a8ed7371cc5b1569
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62175
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit f89cb241ee introduced a regression where the RcompTarget was
not updated according to the SPD.
Change-Id: I07715224b11937604b107e370d957745b245ddd9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64239
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Clang does not like static asserts on integral constant expressions.
Change-Id: If5890a357ed95153d8ae2efa727c111b05bc6455
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This patch does the following:
- Allow selecting 64bit from Kconfig
- Fix up integer to pointer conversion that gcc complains about
- Add a buildtest target in configs
Tested on Thinkpad X200: boots fine to the payload
Change-Id: Icb9c31a28ee231b87109b19c00ce2f8b48b5aefe
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This was dead code as it was checking for the wrong bit (bit 11
indicates the use of shadow GTT). It was doing it at the wrong place
regardless as no BARs are set up.
Move the code clearing GTT into the GMA .init code and do it
unconditionally: if the GTT does not match 2M then the cycles are
simply not decoded.
Tested on thinkpad X200.
Change-Id: Iac3264d484e66e9ca4b3cd3df90ad87a476e31ce
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Linux complained that the numbers in DSDT (256) don't match with the
values in MMCONF (64).
Change-Id: I2ccac64934e8d284e68945f86ec46cb2bf896277
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64260
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Linux needs to know that allocating BARs above 4G is fine so reserve a
region in ACPI for that.
Tested on thinkpad X200: a PCIe window gets allocated above 4G and
Linux does not relocate it.
Change-Id: I62a8a656481eba01add3d7d06b42e3352206df1b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64094
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Enable MKBP (Matrix Keyboard Protocol) interface for all skyrim family
to use for buttons and switches. Disable TBMC (Tablet Mode Switch
device), as it is not needed anymore.
BUG=b:230682161
TEST=manual test on Skyrim:
Volume Up/Down and Power buttons, Tablet Mode switch
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I79ee2fdbb325491c9e3df5b9cff0c0c1181a7001
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Implement sub-function 1 (Get Device Constraints)
of the Low Power S0 Idle Device-Specific Method (_DSM).
This provides a way in which to describe various devices required
D-states to enter LPM (S0ix). The information can be used to help
in diagnostics and understanding of S0ix entry failure.
Values were derived from Intel document 595644 (rev 0.45) and
the ADL FSP sample ASL.
This implementation adds support for ADL. Other SoC's could be
ported to be included as well. If they aren't, they will default
to the existing behavior of a single hardcoded device to ensure
compatibility with Windows.
TEST=Built and tested on brya by verifying SSDT contents
Change-Id: Ibe46a0583c522a8adf0a015cd3a698f694482437
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63969
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Lance Zhao
This board never made it to production, and development on it has long
since stopped; it is a maintenance burden, therefore drop it from the
tree.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ieb12a95ff56c3437cb88df8ef3f6ae115ad53446
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Kane Chen