Commit Graph

17791 Commits

Author SHA1 Message Date
Andrey Petrov 42c4e886c8 drivers/intel/fsp2_0: Add SiliconInit API
This adds SiliconInit API that is needed to be called after memory
has been trained. This call is needed to let the blob do various
initialisations of IP blocks.

Change-Id: I35e02f22174c8392e55ac869265a19c4309932e5
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13799
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-08 13:44:26 +01:00
Andrey Petrov 465fc13c0e drivers/intel/fsp2_0: Add MemoryInit API
This adds implementation of fsp_memory_init() that is used to train
memory.

Change-Id: I72268aaa91eea7e4d4f072d70a47871d74c2b979
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13798
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-08 13:43:04 +01:00
Antonello Dettori 6321d7c14b roda/rk9: Remove #include early_serial.c from romstage
Remove dependency on early_serial.c and instead use the
Super I/O's header to access the functions needed.
Also re-organize some of the superio code in order
to succesfully compile the rom.

Change-Id: I85a6f1352ae3b91c3c98e4d3fa0b90b87e02babc
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/13925
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-08 13:41:03 +01:00
Martin Roth 2a3434757e MAINTAINERS: Add Timothy Pearson to the maintainers list
Change-Id: Ic0ae87ca1fff6d912702190d3fe8ab21285c8630
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13920
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2016-03-07 20:06:33 +01:00
Ben Gardner 2ae9cce87a intel/fsp_baytrail: use 20K PU/PD for GPIO
The E3800 datasheet only lists 2K and 20K Pull Strength for the GPIOs.
The 10K and 40K values map to 'reserved'.

This brings the code closer to the non-FSP baytrail.

Change-Id: I77078bdbbccc00976525dc43fb98f5b2e79eae03
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: https://review.coreboot.org/13907
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-07 04:24:57 +01:00
Lee Leahy fba78bf897 soc/intel/quark: Split out MTRR support
Split out the MTRR support into a new module: mtrr.c.

TEST=Build and run on Galileo

Change-Id: Ib9ec479d171dbbc062509e14fbe246f6d90e903a
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13895
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-07 04:20:22 +01:00
Lee Leahy 6d3cd08252 mainboard/intel/galileo: Enable SD flash cards
Turn on the SD controller to allow it to claim resources.

Testing on Galileo:
*  Edit the src/mainboard/intel/galileo/Makefile.inc file:
   *  Add "select ADD_FSP_PDAT_FILE"
   *  Add "select ADD_FSP_RAW_BIN"
   *  Add "select ADD_RMU_FILE"
*  Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
*  Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
*  Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
*  Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate
UEFIPAYLOAD.fd
*  Edit .config file and add the following lines:
   *  CONFIG_PAYLOAD_ELF=y
   *  CONFIG_PAYLOAD_FILE="path to UEFIPAYLOAD.fd"
*  Testing successful when at the UEFI shell prompt:
   *  After issuing:
      *  "connect -r"
      *  "map -r"
   *  The "dir" command displays the contents of the SD flash card
   *  The "drivers" command shows an SD host and SD media connection

Change-Id: I883dc87270045786ddb931bea83fc36646a128e6
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13894
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-07 04:18:03 +01:00
Lee Leahy fcfa94d6e8 Documentation/Intel: Add EDK-II links
Add a link to the "Driver Writer's Guide" and a link to the "EDK II
firmware for Intel Quark SoC X1000" document.

TEST=None

Change-Id: I8d629d06accfe24a0b8971b5b5868849587c3db7
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13893
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2016-03-07 04:17:34 +01:00
Lee Leahy 7b209ddea7 Documentation/Intel: Making a bootable SD card
Add a link to "Making a bootable SD card"

TEST=None

Change-Id: I5682fdd51a4ba37f97ad35475e11d9843f1498fb
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13892
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-07 04:16:55 +01:00
Martin Roth be63a24c4c BuildSystem: Add Memtest86+ as a secondary payload
This allows memtest86+ to be added to CBFS as a 'secondary'
payload on x86 systems, to be loaded by the main payload
if desired.

Selecting this option, which defaults to no, builds the memtest86+
payload and adds it to CBFS as `img/memtest` which can then be
loaded by for example SeaBIOS or GRUB.

Change-Id: Iecf876aaf588ba1df7abdf6668cb26f089bf5f42
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13858
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Ben Gardner <gardner.ben@gmail.com>
2016-03-05 22:57:53 +01:00
Martin Roth f7fd63066f tpm/acpi/tpm.asl: Only include tpm.asl if tpm is enabled
If the TPM code isn't getting built in, the Kconfig symbol
CONFIG_TPM_TIS_BASE_ADDRESS doesn't exist.  This ends up creating
an invalid operating region in the ACPI tables, causing a bluescreen
in windows.

This should fix this issue:
https://ticket.coreboot.org/issues/35
"commit 85a255fb (acpi/tpm: Gracefully handle missing TPM module)
breaks Windows"

Change-Id: I32e0e09c1f61551a40f4842168f556d5e1940d28
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13890
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-05 22:51:03 +01:00
Andrey Petrov 73f7069fe6 arch/x86: Add common assembly code for stages that run in CAR
This adds a few assembly lines that are generic enough to be shared
between romstage and verstage that are ran in CAR. The GDT reload
is bypassed and the stack is reloaded with the CAR stack defined
in car.ld. The entry point for all those stages is car_stage_entry().

Change-Id: Ie7ef6a02f62627f29a109126d08c68176075bd67
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13861
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-03-05 20:11:35 +01:00
Andrey Petrov dd56de974d arch/x86: document CAR symbols and expose them in symbols.h
Attempt to better document the symbol usage in car.ld for
cache-as-ram usage. Additionally, add _car_region_[start|end]
that completely covers the entire cache-as-ram region. The
_car_data_[start|end] symbols were renamed to
_car_relocatable_data_[start|end] in the hopes of making it
clearer that objects within there move. Lastly, all these
symbols were added to arch/symbols.h.

Change-Id: I1f1af4983804dc8521d0427f43381bde6d23a060
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13804
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-03-05 16:00:42 +01:00
Martin Roth b1bca88a04 lint-kconfig: pipe stderr to stdout to catch script errors
Because the perl error messages go to stderr, we were not catching these
on the build server.  If the script has an issue, we want to know
immediately, so change the bash script that calls into the perl lint
tool to pipe these to stdout.

Change-Id: Ieeec9ccbd59177cfd1859a9738a4ee1fab803d28
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13877
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-05 15:40:31 +01:00
Antonello Dettori bc839fba3d amd/thatcher: Removed #include early_serial.c from romstage
Remove dependency on early_serial.c and instead use the
Super I/O's header to access the functions needed.

Change-Id: I9edf7fc2501aa832106dda9213e702dbcc1200b4
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/13887
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
2016-03-05 15:38:40 +01:00
Patrick Rudolph 98b5f907ac include/device/dram: Fix DDR3-1866
The PLL multiplier value is off by one for DDR3-1866 due to a
wrong TCK value, resulting in DDR3-1600 being used by the PLL.

Needs test on real hardware !

Change-Id: I657b813889945f0d9990dd11680a3d3a25b53467
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/13613
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-05 15:35:14 +01:00
Iru Cai 8e7928a6fe sandybridge/gma_lvds: support both Sandy&Ivy on one board
Sandy and Ivy Bridge processors use the same socket, and a mainboard
with the socket can support both types of CPUs. However, they use
different native graphics init code for LVDS and cause a crash if
running the wrong code.

This change detects the CPU type and then selects the right code to
run. It will add some more code in ramstage. It also merges the
{SANDY,IVY}BRIDGE_LVDS symbol to one SANDYBRIDGE_IVYBRIDGE_LVDS.

Tested on a Lenovo T520 with i7-2630qm and i7-3720qm

Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Change-Id: I4624759f9c92d56d547db1ab4b9a1d611a182a91
Reviewed-on: https://review.coreboot.org/12087
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Tested-by: build bot (Jenkins)
2016-03-05 09:39:41 +01:00
Vladimir Serbinenko 42f42ff450 Hide EC_GOOGLE_CHROMEEC_SPI_BUS.
It's mobo architecture, not a user-adjustable setting.

Change-Id: I8bb81638f391cf0ba880801e4707d8f0957897c8
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13906
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-05 00:57:22 +01:00
Vladimir Serbinenko ca1b2d19a9 lz4_wrapper: Use __asm__ rather than asm.
__asm__ is more robust to compilation flags.

Change-Id: Ic7ca6e38ddd439dcfc4a62ef272ecea62416b4be
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13905
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
2016-03-05 00:56:53 +01:00
Vladimir Serbinenko d51a0896c6 Kconfig: hide useless options on ARM.
Those options have no effect or lead to compile error on ARM due
to fundamental incompatibilities. Add proper "depends on" clauses
to hide them.

Change-Id: I860fbd331439c25efd8aa92023195fda3add2e2c
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13904
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-05 00:56:36 +01:00
Martin Roth ab8f923f53 toolchain.inc: test IASL by version string instead of number
Test that the coreboot toolchain version of IASL is being used by
looking for the string 'coreboot toolchain' instead of a specific
version number.  While this may cause people to have to rebuild
their toolchains again now, it helps to prevent toolchain failures
when bisecting in the future.

Change-Id: I9913eeae8f29ddc3ec8c70077c05d898595eb283
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12847
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-04 16:36:25 +01:00
Martin Roth ca55f0a0ea util/futility: trivial - Add distclean target
The what-jenkins-does build runs distclean when building the utilities.
It doesn't fail the build if distclean fails, but it generates a
scary warning.

Change-Id: Iac90958951976ed326a89ef2b5f2d9f17f9f2d6b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13888
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-04 16:17:10 +01:00
Aaron Durbin 8198c678f7 arch/x86: always use _start as entry symbol for all stages
Instead of keeping track of all the combinations of entry points
depending on the stage and other options just use _start. That way,
there's no need to update the arch/header.ld for complicated cases
as _start is always the entry point for a stage.

Change-Id: I7795a5ee1caba92ab533bdb8c3ad80294901a48b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13882
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-03-04 04:49:46 +01:00
Aaron Durbin 4330a9c8e5 arch/x86: rename reset_vector -> _start
In order to align the entry points for the various stages
on x86 to _start one needs to rename the reset_vector symbol.
The section is the same; it's just a symbol change.

Change-Id: I0e6bbf1da04a6e248781a9c222a146725c34268a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13881
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-03-04 01:16:05 +01:00
Andrey Petrov ccd300b4b4 arch/x86: Allow soc/chipset to set linking address
Until recently x86 romstage used to be linked at some default
address. The address itself is not meaningful because the code
was normally relocated at address calculated during insertion
in CBFS. Since some newer SoC run romstage at CAR it became
useful to link romstage code at some address in CAR and avoid
relocation during build/run time altogether.

Change-Id: I11bec142ab204633da0000a63792de7057e2eeaf
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13860
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-03-03 23:56:01 +01:00
Aaron Durbin f8468d43e0 cpu/x86/16bit: rename _start -> _start16bit
In order to avoid collisions with other _start symbols while
grepping and future ones be explicit about which _start this
one is: the 16-bit one only used by the reset vector in the
bootblock.

Change-Id: I6d7580596c0e6602a87fb158633ce9d45910cec2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13880
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2016-03-03 23:53:14 +01:00
Aaron Durbin 0fd068b3c3 cpu/x86/16bit/reset16: mark reset vector executable
It's helpful to see the reset vector in objdump output. Without
it being marked executable it doesn't get displayed.

Change-Id: I85cb72ea0727d3f3c2186ae20b9c5cfe5d23aeed
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13879
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2016-03-03 23:52:50 +01:00
Aaron Durbin 998d8561d1 cpu/x86/16bit/reset16: remove stale 32-bit jump
Patrick at least indicated this jump after the reset
vector jump was a remnant from some construct used long
ago in the project. It's not longer used (nor could I find
where it was). Therefore, remove it.

Change-Id: I31512c66a9144267739b08d5f9659c4fcde1b794
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13878
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2016-03-03 23:52:31 +01:00
Andrey Petrov 9738970c15 drivers/intel/fsp2_0: Add utility functions
This adds a set of utility functions that help load and identify
FSP blobs.

Change-Id: I1d23f60fd1dc8de7966142bcd793289220a1fa5e
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13797
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-03 21:26:28 +01:00
Andrey Petrov b37fd67e87 drivers/intel/fsp2_0: Add coreboot<->FSP header files
This adds important header files that specify calling interface between
coreboot and FSP.

Change-Id: I393601c91e3c3f630e0fc899f1140ecefed8ecba
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13796
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-03 21:26:21 +01:00
Martin Roth 0e6c0e18e3 kconfig_lint: make sure if and endif statements are balanced
In Kconfig files, the 'if' and 'endif' statements need to match up. A
file can't start an if statement that's completed in the next file.

Add a check as the files are being parsed to make sure that they match
up correctly.

Change-Id: If51207ea037089ab84c768e5a868270468cf4c4f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13876
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-03 20:42:49 +01:00
Patrick Rudolph b97009ed43 nb/intel/sandybridge/raminit: Fill SMBIOS type17 info
Fill minimal info required for SMBIOS type 17.
Report
 * DIMM size
 * channel
 * rank per DIMM
 * speed in Mhz
 * DIMM type
 * slot
 * manufacturer ID
 * serial

Allows dmidecode to print the current RAM configuration.

Test system:
 * Gigabyte GA-B75M-D3H
 * Intel Pentium CPU G2130
 * Linux 4.3
 * dmidecode 3.0

dmidecode output:
Handle 0x0005, DMI type 17, 40 bytes
Memory Device
	Array Handle: 0x0000
	Error Information Handle: Not Provided
	Total Width: 16 bits
	Data Width: 8 bits
	Size: 8192 MB
	Form Factor: DIMM
	Set: None
	Locator: Channel-0-DIMM-0
	Bank Locator: BANK 0
	Type: DDR3
	Type Detail: Synchronous
	Speed: 1600 MHz
	Manufacturer: Unknown (cd04)
	Serial Number: None
	Asset Tag: Not Specified
	Part Number: F3-1866C9-8GSR
	Rank: 2
	Configured Clock Speed: 1600 MHz
	Minimum Voltage: Unknown
	Maximum Voltage: Unknown
	Configured Voltage: Unknown

Handle 0x0006, DMI type 17, 40 bytes
Memory Device
	Array Handle: 0x0000
	Error Information Handle: Not Provided
	Total Width: 16 bits
	Data Width: 8 bits
	Size: 8192 MB
	Form Factor: DIMM
	Set: None
	Locator: Channel-1-DIMM-1
	Bank Locator: BANK 0
	Type: DDR3
	Type Detail: Synchronous
	Speed: 1600 MHz
	Manufacturer: Unknown (cd04)
	Serial Number: None
	Asset Tag: Not Specified
	Part Number: F3-1866C9-8GSR
	Rank: 2
	Configured Clock Speed: 1600 MHz
	Minimum Voltage: Unknown
	Maximum Voltage: Unknown
	Configured Voltage: Unknown

Change-Id: I4e5f772d68484b9cb178ca8a1d63ad99839f3993
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/13852
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-03 20:42:11 +01:00
Patrick Rudolph 076915955f src/device/dram/ddr3: Parse additional information
Parse manufacturer id and ASCII serial.
Required for SMBIOS type 17 field.

Change-Id: I710de1a6822e4777c359d0bfecc6113cb2a5ed8e
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/13862
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-03 20:42:00 +01:00
zbao c3a08a9d5e amdfwtool: Fix some PSP2 issues
1. Change the function which integrated one firmware, to the function
   which pushes the whole group. Use fw_table as a parameter instead
   of using the global table name.
2. Let PSP2 and PSP1 not dependent on the other. It turns out PSP2
   can exist without PSP1. For some APU, the PSP directory has to be
   put in PSP2 field (ROMSIG 0x14).
3. Reserve 32 more bytes in PSP2 header. It is defined by spec. It
   is tested, and it is true.

These above changes are overlapping, hard to split them. Sorry.

Change-Id: I834630d9596d7fb941e2cad5d00ac3af04a537b5
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/13808
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-03 12:03:03 +01:00
Werner Zeh ebf732b4a5 cbfstool: Use fixed width data types for e820entry struct.
In e820entry struct, the members are defined using
standard types. This can lead to different structure size
when compiling on 32 bit vs. 64 bit environment. This in turn
will affect the size of the struct linux_params.
Using the fixed width types resolves this issue and ensures
that the size of the structures will have the same length
on both 32 and 64 bit systems.

Change-Id: I1869ff2090365731e79b34950446f1791a083d0f
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/13875
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-03-03 06:19:25 +01:00
Werner Zeh bbf508914d cbfstool: Initialize contents of linux_params to 0
When linux is used as payload, the parameters to the kernel are build
when cbfstool includes bzImage into the image. Since not all
parameters are used, the unused will stay uninitialized.
There is a chance, that the uninitialized parameters contain
random values. That in turn can lead to early kernel panic.
To avoid it, initialize all parameters with 0 at the beginning.
The ones that are used will be set up as needed and the rest
will contain 0 for sure. This way, kernel can deal with the
provided parameter list the right way.

Change-Id: Id081c24351ec80375255508378b5e1eba2a92e48
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/13874
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-03 06:18:23 +01:00
Stefan Reinauer 266b5171a3 buildgcc: Bump version to 1.36
Numerous changes have gone in since the last bump, let's increase
the version.

Change-Id: Ie3ae8c24b26bd22b70bc5ddf5c1125b5b1d3a021
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/13873
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-03-03 04:23:25 +01:00
Patrick Rudolph 9f3f9154c9 nb/intel/sandybridge/romstage: Read fuse bits for max MEM Clk
Instead of hardcoding the maximum supported DDR frequency to
800Mhz (DDR3-1600), read the fuse bits that encode this information.

Test system:
 * Intel IvyBridge
 * Gigabyte GA-B75M-D3H

Change-Id: I515a2695a490f16aeb946bfaf3a1e860c607cba9
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/13487
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-02 21:46:49 +01:00
Patrick Rudolph 2bdeb7f843 src/arch/x86/smbios: Add vendors
Add more manufacturer IDs for vendor:
* GSkill
* OCZ
* Transcend

Change-Id: Ic7df76b1310b2c1abea9c5d2d8fd688cb2a713b8
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/13863
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-03-02 21:39:15 +01:00
Patrick Rudolph 77e45d3ecc nb/intel/sandybridge/raminit: Make discover_timC_write non cyclic
The code can't handle cyclic zero runs. Make sure it will never
wrap around by setting the top-most bit to constant one.

Fixes "Mini channel test failed (2)".

Test system:
 * Gigabyte GA-B75M-D3H
 * Intel Pentium CPU G2130

Change-Id: I55e610d984d564bd4675f9318dead6d6c1e288a3
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/13853
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-02 21:38:28 +01:00
Martin Roth 58c68d56de crossgcc: add 'urls' option to print urls of all packages
This should allow the builder to download the packages securely.

Change-Id: If5feeff85bd551cbe08849421197d11cc2432d1e
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13867
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-02 19:11:01 +01:00
Martin Roth 4a53db06ec buildgcc: Add 'nocolor' option to remove color codes from output
When writing to a logfile, the color codes just make things confusing.
The --nocolor option will allow these to not be printed.

Change-Id: I67645aac20b420ac83b828e77e0e50aab88d3d47
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13866
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-02 18:57:10 +01:00
Stefan Reinauer 9b1936dc82 buildgcc: Use $(CURDIR) instead of $(PWD)
coreboot's top level Makefile does the same, so let's stay consistent.

Change-Id: I9e995f3ecadd05d6fbfda64b45dee3a9900d9189
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/13869
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-02 18:53:19 +01:00
Stefan Reinauer ed5642234a abuild: Use 12 lines of context for errors
The current default of 6 lines leaves us with no context
about the actual error:

*** ERROR: 3 warnings encountered, and warnings are errors.

coreboot-gerrit/util/kconfig/Makefile:38: recipe for target 'oldconfig' failed
make[1]: *** [oldconfig] Error 1
make[1]: Leaving directory 'coreboot-gerrit'

Change-Id: I67e7d740e7b3b1c66005dc1bf50557a20bc15428
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/12720
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-02 18:38:32 +01:00
Stefan Reinauer c77e041909 buildgcc: Disable RISC-V GDB
Our GDB doesn't support RISC-V yet, so let's disable it for now
to keep the build from breaking.

Change-Id: Iecc6d97fb16d16410c56965abeea55c67800f220
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/13872
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-03-02 18:33:37 +01:00
Stefan Reinauer 163506a8f6 buildgcc: Allow specifying destination directory
With this change you can say

 $ make DEST=/opt/cross-1.35

to get all of the cross toolchain built and installed to /opt/cross-1.35

Change-Id: Icc3e605c4824bfa2831d030e4ed9dd0331ff722f
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/13847
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-01 21:48:20 +01:00
Stefan Reinauer b7c40630d9 buildgcc: Fix building GDB for mipsel-elf
Change-Id: I31ed159b13c0da60383068832615c6e4a9608efe
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/13849
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-01 21:26:34 +01:00
Ronald G. Minnich fb944f4270 crosstool: add EXPAT as a dependency on the gdb build.
qemu-power8 wants to tell about itself with XML, and so
we need to build gdb with EXPAT so it can understand XML.

Change-Id: I460e27f883956ed5d54e6070916e2682ee0f7a1b
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/13846
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-01 21:25:25 +01:00
Subrata Banik b7e69a2e56 Skylake: Support Intel Speed Shift Technology based on config
Intel Speed Shift Technology is a new mechanism that replaces
Legacy P-state. ISST allows OS hints about energy/performance
preference. H/W performs the actual P-state control (autonomous)

1. Optimization frequency seclection for low residency workloads,
no longer a static knee point.
2. Optimized frequency selection for best energy to performance
trade offs.
3. Kick down frequency (from idle) fpr best responsiveness while
taking energy consumption init account.

Coreboot's responsiblity is to configure MSR 0x1AA ISST_EN bits
which will reflect in CPUID.06h:EAX[Bit 7] that driver checkes
and enable HWP accordingly.

BUG=chrome-os-partner:47517
BRANCH=None
TEST=Booted kunimitsu and verify HWP getting enabled/disabled
using Intel P-state driver.

Change-Id: I91722aa1077f4ef6c8620b103be3e29cfcd974e5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: aa7d004cb2e19047e4434e3e2544cf69393ce28f
Original-Change-Id: Ie617da337babde7f196a7af712263e37f7eed56f
Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/313107
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Wenkai Du <wenkai.du@intel.com>
Reviewed-on: https://review.coreboot.org/13835
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-01 20:57:45 +01:00
Subrata Banik 2a696c07b9 Skylake boards: Enabling HWP (hardware P state control)
This patch provides config options to enable/disable Intel SST
(Speed Shift Technology).

BUG=chrome-os-partner:47517
BRANCH=None
TEST=Booted kunimitsu/lars, verified HWP driver load successfully.

CQ-DEPEND=CL:313107

Change-Id: I9419a754384f96d308a5ac2ad90bbb519edc296e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 5efb7978e9d3ca9a709a4793ad213423a1c3c45d
Original-Change-Id: I328b074b4f56ebe3caa8952ce3df7f834c1cf40f
Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/326650
Original-Tested-by: Wenkai Du <wenkai.du@intel.com>
Original-Reviewed-by: Benson Leung <bleung@chromium.org>
Reviewed-on: https://review.coreboot.org/13843
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-01 20:54:34 +01:00