Commit Graph

41571 Commits

Author SHA1 Message Date
Felix Held 349a145299 soc/amd/picasso/acp: rename acp_update32 mask parameters
The name of the and_mask parameter was a bit misleading, due to the
function inverting the value. Renaming this into clear and set makes it
more obvious what those parameters will actually do.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If307ab4858541861e22f8ff24ed178d47ba70fe5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52524
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-21 03:18:41 +00:00
Julius Werner c893197352 commonlib/region: Turn addrspace_32bit into a more official API
We had the addrspace_32bit rdev in prog_loaders.c for a while to help
represent memory ranges as an rdev, and we've found it useful for a
couple of things that have nothing to do with program loading. This
patch moves the concept straight into commonlib/region.c so it is no
longer anchored in such a weird place, and easier to use in unit tests.
Also expand the concept to the whole address space (there's no real need
to restrict it to 32 bits in 64-bit environments) and introduce an
rdev_chain_mem() helper function to make it a bit easier to use. Replace
some direct uses of struct mem_region_device with this new API where it
seems to make sense.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ie4c763b77f77d227768556a9528681d771a08dca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-04-21 02:06:26 +00:00
Felix Singer b03e497ef1 soc/intel/cannonlake/romstage: Reuse device pointer
Reuse `dev` pointer for SmbusEnable configuration and remove `smbus`
pointer.

Change-Id: I7ad7cdeb632eb52ae02b60ca51e7d4845dffdb0d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-20 19:13:09 +00:00
Felix Singer 2a3689f0e4 soc/intel/cannonlake: Deduplicate function declaration
Move the function declaration of parse_devicetree() out of the if-else
preprocessor condition.

Change-Id: I6974554711e4cc2bb944bff14fc057ef6945c888
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-20 19:13:02 +00:00
Felix Singer 0a6cf23ce7 soc/intel/cannonlake: Remove unnecessary function
parse_devicetree() just calls parse_devicetree_param(). To be aligned
with other platforms, remove it and rename parse_devicetree_param() to
parse_devicetree().

Change-Id: I1128ab709cfdb02bbdb505c3f22f5433a30cb3c1
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52488
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-20 19:12:47 +00:00
Felix Singer 78976c153a mainboard: Drop redundant DEVICETREE configuration
`devicetree.cb` is the default value for the Kconfig DEVICETREE
setting. Drop redundant configurations.

Change-Id: I5eded3d5e38ca80986da2fda95050815c2702f82
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52504
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-20 18:02:23 +00:00
Angel Pons e934be2215 mb/asrock/h110m: Choose `CHIPSET_LOCKDOWN_COREBOOT`
The `chipset_lockdown` option defaults to `CHIPSET_LOCKDOWN_FSP` if
omitted. As most of the mainboards use `CHIPSET_LOCKDOWN_COREBOOT`,
choose it here as well for consistency.

Change-Id: I5ef61f3d931abdb740411d8c58048cf21185802c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52094
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2021-04-20 16:36:04 +00:00
Patrick Rudolph 62e3895bba mb/prodrive/hermes: Fix HSI version
Fix board ID (HSI) read from BMC:
* R02 and R03 have an HSI of 2.
* R04 has an HSI of 3.

Change-Id: I987b2dd848c48e3562bcc07270c958cde3c5a962
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51920
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-20 16:23:38 +00:00
Felix Held 4b6773a652 vc/amd/fsp/cezanne: update SMU setting section of FspmUpd.h
There was a bug in the UPDs for STAPM settings that required one UPD
field to be extended from 8 to 32 bits, so this patch is a breaking
change to the binary layout, but since the UPD struct fields for the SMU
SoC power and performance tuning parameters aren't populated by the
coreboot code yet and we added some padding after each logical section
in the UPD, this isn't expected to cause too much trouble; the only
thing that is required is that a very recent build of the FSP binaries
need to be used in combination with the new coreboot code that will
populate the struct fields in follow-up patches.

BUG=b:182297189

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If39aaf64e8e1b4c0426f22ce8ed07707c2a31e61
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-04-20 15:50:15 +00:00
Angel Pons 8f3e1192df soc/intel/skylake: Move `SataTestMode` to Kconfig
This option is not mainboard-specific, and should be user-visible.

Change-Id: I9ff2ca984cd238a112af4efd7685f142cc6e5459
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-20 09:19:20 +00:00
Raul E Rangel dfe3a2fcfc soc/amd/{common,cezanne}: Add uPEP device
The uPEP device is required to support S0i3. The device has been written
in ASL to make it easier to read and maintain. The device constraints
are purely informational. We use a dummy constraint like the Intel
platforms to keep both linux and Windows functional.

In order for this device to be used by the linux kernel the
ACPI_FADT_LOW_PWR_IDLE_S0 flag must be set. So including it
unconditionally doesn't cause any problems.

The AMD Modern Standby BIOS Implementation Guide defines two UUIDs,
one for getting the device constraints, and one for handling
notifications. This differs from the Intel specification and the linux
driver implementation. For this reason I haven't implemented any of the
notification callbacks yet.

BUG=b:178728116
TEST=Boot OS and verify _DSM is called:
[    0.226701] lps0_device_attach: ACPI: \_SB_.PEP_: _DSM function mask: 0x3
[    0.226722] lpi_device_get_constraints_amd: ACPI: \_SB_.PEP_: _DSM function 1 eval successful
[    0.226723] lpi_device_get_constraints_amd: ACPI: \_SB_.PEP_: LPI: constraints list begin:
[    0.226724] lpi_device_get_constraints_amd: ACPI: \_SB_.PEP_: LPI: constraints list end

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I2deef47eabe702efe1a0f3747c9f27bcec37464b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52445
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-20 01:10:54 +00:00
Angel Pons b922cbbdd6 device/azalia_device.c: Add option to lock down GCAP
On Intel 6-series PCHs, the GCAP register is R/WO (Read / Write Once),
and needs to be written to after the HD Audio controller is taken out
of reset. Add a Kconfig option to read and write back GCAP in order to
lock it down. Follow-up commits will select this option when switching
platforms to use common Azalia code, to preserve original behaviour.

Change-Id: I70bab20816fb6c0bf7bff35c3d2f5828cd96172d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-04-19 19:02:08 +00:00
Angel Pons 6b89746644 soc/intel/common/block/smm: Drop stale comment
This comment is most likely a copy-paste leftover from Braswell.

Change-Id: I49bfa3cc56539df0b47d2e2bd74b2bfc45421034
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52500
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-19 14:50:35 +00:00
Felix Singer df5a6b36b8 mb/clevo/cml-u/Kconfig: Use BOARD_CLEVO_L140CU_BASE
To make the L140CU able to be selected by other OEMs, use
BOARD_CLEVO_L140CU_BASE for OEM independent options.

BOARD_CLEVO_L140CU represents the standard Clevo mainboard without any
OEM modifications, while BOARD_CLEVO_L140CU_BASE is used for the
baseboard.

Change-Id: Iee82eadebfc851619dbb64de09283c5ee55a499f
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52241
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-19 14:08:34 +00:00
Nikolai Vyssotski 4e29e2f14b mb/amd/majolica: use GPIO_40 as reset pin for NVME SSD
Default Majolica configuration uses GPIO_40 for NVME M2_SSD_RST#

BUG=b:182100027
TEST=ls /dev/nvme*

Change-Id: Idecc0ec7eaf903b29fea109d3688f3c249da62f5
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-04-19 14:06:32 +00:00
Jakub Czapiga 48b0079000 lib/rtc: Fix incomplete leap year macro
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Found-by: Paul Fagerburg <pfagerburg@chromium.org>
Change-Id: Ic434c969141c67ce317a5db0c8805de02c84eb08
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-04-19 13:04:58 +00:00
Angel Pons ac9af1adb9 sb/intel/common: Drop some PCH_LPC_DEV macros
The macro definitions depend on __SIMPLE_DEVICE__ and are only used in
the get_gpio_base() or lpc_get_pmbase() functions, which already guard
PCH_LPC_DEV usage using __SIMPLE_DEVICE__ in preprocessor.

Change-Id: I5d3681debe29471dfa143ba100eb9060f6364c93
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-19 10:45:23 +00:00
Angel Pons 0db4b27c7d soc/intel/baytrail/pmutil.c: Define __SIMPLE_DEVICE__
Change-Id: I0d5fa4451b356970cf9843a76d0fa4d2af4307da
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52460
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2021-04-19 10:45:15 +00:00
Angel Pons 5595a20f39 soc/intel/braswell/pmutil.c: Define __SIMPLE_DEVICE__
Change-Id: I2caa9cbb812e17f041c15654aef756e41fb71398
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52459
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2021-04-19 10:45:06 +00:00
Angel Pons 6205e03828 soc/intel/common/block/pcr: Define __SIMPLE_DEVICE__
Change-Id: I06f9c623947e48a7213e42507f4da51c12b425d7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-19 10:44:59 +00:00
Angel Pons 8a10aff35a soc/intel/cannonlake/elog.c: Define __SIMPLE_DEVICE__
Change-Id: Ie2f02b9934d843c29d17a72a6bf3b2bae91ce8d1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-19 10:44:53 +00:00
Angel Pons fc8e997caa soc/intel/braswell/smbus.c: Define __SIMPLE_DEVICE__
Change-Id: Ic16fd74d4ddf96e29bcdada671dab0e590af74ef
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2021-04-19 10:44:40 +00:00
Felix Singer 1ee8e8e0de mb/clevo/cml-u: Rename `BOARD_CLEVO_L140CU_OPTIONS`
Rename `BOARD_CLEVO_L140CU_OPTIONS` to `BOARD_CLEVO_L140CU_BASE` to
make clear that this option represents the baseboard.

Change-Id: I76690626fddafc8e3c37ef760aeb4f064fb6b591
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52480
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-19 10:11:18 +00:00
Felix Singer 7dc57159fe mb/clevo/kbl-u: Move memory init config to variant level
Memory init config is board specific. Thus, move it to variant level and
hook up variant romstage.c.

Change-Id: Id78788815ad9c4ed64f0172fb746ff6e50d608ef
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-19 10:11:09 +00:00
Felix Singer 8434d92c30 mb/clevo/kbl-u: Clean up code
Change-Id: I98d806ebf126522689b2c101b75add733825fcf1
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-19 10:10:30 +00:00
Felix Singer cbfcb2a6bb mb/clevo/l140cu: Move FSP-M config hook to mainboard level
Hook up FSP-M configuration on mainboard level instead of variant level
being able to do common configuration there.

Also, hook up variant romstage.c on mainboard level for variant
specific configurations.

Change-Id: Ic161f83cb629b1e70ca670e10975a25bc0949656
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-19 10:10:20 +00:00
Angel Pons 24f4623384 soc/intel/common/block/smbus: Define __SIMPLE_DEVICE__
Change-Id: I93f7918763d87f8fb50f39f9469694e73aeff37b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-19 06:41:53 +00:00
Sugnan Prabhu S 60be9dbbc7 drivers/intel/mipi_camera: Adding support for low power camera probe
Add a new configuration low_power_probe to avoid camera privacy LED
blink during the boot.

Change-Id: I27d5c66fb380ae6cd76d04ee82b7736407dac1b0
Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com>
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52189
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-19 06:40:03 +00:00
Marc Jones 194179c3d7 mainboard/ocp/tiogapass: Remove redundant PARALLEL_MP_AP_WORK
PARALLEL_MP_AP_WORK is set in the xeon_sp Kconfig. No need to
set it here.

Change-Id: I66d59fd7cbc3617eb739fdf2f3750f20ee701fbd
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-19 06:38:18 +00:00
Arthur Heymans 29abd048ef cpu/x86/smm/smm_module_loaderv2.c: Rename file
As v1 was dropped, rename v2.

Change-Id: I4dd51804e9391284c7624c42ad8180a14b1a4c84
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-19 06:36:43 +00:00
Arthur Heymans 88407bcd9d cpu/x86/smm: Drop the V1 smmloader
Change-Id: I536a104428ae86e82977f2510b9e76715398b442
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-19 06:36:28 +00:00
Arthur Heymans e6c3523b1b cpu/x86/smm_loaderv2: Use the permanent stack top during relocation
Use the same stack location during relocation as for the permanent
handler.

When the number of CPUs is too large the stacks during relocation
don't fit inside the default SMRAM segment at 0x30000. Currently the
code would just let the CPU stack base grow downwards outside of the
default SMM segment which would corrupt lower memory if S3 is
implemented.

Also update the comment on smm_module_setup_stub().

Change-Id: I6a0a890e8b1c2408301564c22772032cfee4d296
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-19 06:36:05 +00:00
Karthikeyan Ramasubramanian 110c47699a Revert "mb/google/mancomb: Enable early EC Software Sync"
This reverts commit 8001934141. EC
software sync needs to be enabled in payload once the EFS2 requirements
are met.

BUG=b:185277224
TEST=Build.

Cq-Depend: chromium:2829948
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ib22a89e221e1e057d82ef76b7008e5d3f14df5e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52451
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-19 06:32:03 +00:00
Karthikeyan Ramasubramanian 54888e8d7d Revert "soc/amd/cezanne: Add support to perform early EC sync"
This reverts commit ad7c33abd2. With EFS2
already enabled in EC, enabling early EC sync is not required. Also a
workaround has been added in payload to address any boot issues.

BUG=b:185277224
TEST=Build and boot to OS in Guybrush in both normal and recovery mode.

Cq-Depend: chromium:2832032
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I34f8433739754365c8e5a10fdf7e58e3d1e7e797
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52419
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-19 06:31:53 +00:00
Karthikeyan Ramasubramanian 9605136bc6 Revert "mb/google/guybrush: Enable early EC Software Sync"
This reverts commit 1e36dc078e. With EFS2
already enabled in EC, enabling early EC sync is not required. Also a
workaround has been added in payload to address any boot issues.

BUG=b:185277224
TEST=Build and boot to OS in Guybrush in both normal and recovery mode.

Cq-Depend: chromium:2832032
Change-Id: I921dc5c814e5187dce283eeff43075b59885723a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52418
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-19 06:30:49 +00:00
Nico Huber 1f2b5fb201 libpayload/keyboard: Reset to scancode set #2 on exit
If we select scancode set #1 and keep that, it can confuse Linux
with keyboards that don't return to set #2 when asked to load the
defaults. This happens for instance with various integrated Think-
Pad keyboards but was also seen with an external PS/2 one.

The chosen configuration, scancode set #2 without translation, seems
to be the default for many systems. So we can expect other payloads
and kernels to work with it.

Change-Id: I28d74590e9f04d32bb2bbd461b67f15014f927ec
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47594
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-18 20:45:23 +00:00
Nico Huber 4dc92782fc libpayload/keyboard: Add a detention state
Instead of ignoring keyboards indefinitely when they failed to
initialize, we wait 5s and then start over with the hotplug
detection. As we always assume a present keyboard at first,
we'd otherwise never have a chance to hot plug a device after
the initial 30s timer ran out.

Change-Id: I8dec4921b2e932442d52b5118cdcf27090633498
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-18 20:45:02 +00:00
Nico Huber e97d320df2 libpayload/keyboard: Implement hot (un)plugging
While we assume a keyboard is attached, we send an echo command every
500ms. If there is no data coming from the keyboard within 200ms, we
assume it was detached.

Correspondingly, if we assume no keyboard is attached, we run an echo
command once per second.

Change-Id: I2c75182761729bf30711305f3d8b9d43eafad675
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47593
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-18 20:43:58 +00:00
Jakub Czapiga 5d884837f4 tests: Add lib/coreboot_table-test test case
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I4d7d9ca43316bf514bb5ebd8909f441bcfa20eba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-04-18 20:43:05 +00:00
Matt DeVillier bcc7aaa70c mb/google/hatch: Guard ChromeOS fmd selection on CHROMEOS
Ensure the ChromeOS FMAPs are used only when CONFIG_CHROMEOS
is selected, so non-ChromeOS targets use the default x86 FMAP.

Change-Id: Id5d3e7a44973f2fadba3ea15e0e544eee7fa53e6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-18 20:42:56 +00:00
Eric Lai bc816141c5 mb/google/mancomb: Remove PS/2 mouse config
Sync from guybrush.

BUG=b:182211161
TEST=builds

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I02b375b6fc134e56b7f55e1421f694daa4aa994d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52407
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-18 20:42:27 +00:00
Karthikeyan Ramasubramanian 74e2c98030 mb/google/guybrush/var/guybrush: Add GPIO override table
EN_SPKR is routed to SD pin in the ALC1019 speaker amplifier. The
concerned pin has a voltage rating of 1.8V whereas the EN_SPKR GPIO has
a voltage rating of 3.3 V. The schematics has been updated to bridge the
gap. So enable the speaker amplifier by default and add a gpio override
table to disable the speakers before board version 2.

Also update the codec ACPI HID name for the kernel machine driver to
probe the codec successfully.

BUG=b:182960979
TEST=Build and boot to OS in guybrush. Ensure that the GPIO output state
is high.

Change-Id: I32b29bfae9bc94b5119b33a535d8bc825ef89445
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52355
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-18 20:42:13 +00:00
Karthikeyan Ramasubramanian 63fc236856 mb/google/guybrush: Enable AMD I2S Machine Driver
Enable AMD I2S machine driver and configure the devicetree with HID
information so that the machine driver ACPI objects can be passed to the
kernel.

BUG=b:182960979
TEST=Build and boot to OS in guybrush. Ensure that the ACPI objects for
machine driver is populated.

Change-Id: I8ed474d25273082d1e0742ba93746d97930deb19
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-18 20:42:01 +00:00
Karthikeyan Ramasubramanian 8c5f3ebbdf drivers/amd/i2s_machine_dev: Make DMIC select gpio optional
The selector component in Sound Open Firmware (SOF) can consume all the
mics and use the configuration in the Use Case Manager (UCM) to select
the right channel. Hence dmic select gpio configuration is optional.

BUG=b:182960979
TEST=Build and boot to OS in Guybrush. Ensure that the machine driver
ACPI object is populated without DMIC select GPIO.

Change-Id: Iba00b07c3656c487e33bab184fefee7037745e2d
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52393
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-18 20:41:55 +00:00
Felix Held 90b0701f9a soc/amd/cezanne/Kconfig: add missing ACPI_BERT and ACPI_BERT_SIZE
ACPI_BERT_SIZE is used in the FSP driver and the fsp_m_params.c. The
latter one is planned to be deprecated though.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id1a250defbd31e255df9b7a7dd8488dc3182649b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-18 20:41:21 +00:00
Furquan Shaikh e206e2e7ff soc/intel/cnl and mainboards: Drop `cnl_configure_pads()`
CB:31250 ("soc/intel/cannonlake: Configure GPIOs again after FSP-S is
done") introduced a workaround in coreboot for `soc/intel/cannonlake`
platforms to save and restore GPIO configuration performed by
mainboard across call to FSP Silicon Init (FSP-S). This workaround was
required because FSP-S was configuring GPIOs differently than
mainboard resulting in boot and runtime issues because of
misconfigured GPIOs.

This issue has since been fixed in FSP (verified with FSP v1263 on
hatch). However, there were still 4 boards in coreboot using
`cnl_configure_pads()`. As part of RFC CB:50829, librem_cnl, clevo/cml-u
and system76/lemp9 were tested to ensure that this workaround is no
longer required.

This change drops the workaround using `cnl_configure_pads()` and
updates all mainboards to use `gpio_configure_pads()` instead.

Signed-off-by: Furquan Shaikh <furquan@google.com>
Tested-by: Angel Pons <th3fanbus@gmail.com>
(Tested purism/librem_cnl)
Tested-by: Michael Niewöhner <foss@mniewoehner.de>
(Tested clevo/cml-u which is similar to system76/lemp9)
Change-Id: I7a4facbf23fc81707cb111859600e641fde34fc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52248
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-18 20:41:04 +00:00
Matt DeVillier e794312882 mb/purism/librem_14: Update GPIO config
Update GPIO config based on review of latest schematics:

- LAN/WLAN reset lines are NC
- SDIO lines configured via GPP_G0-G7
- DMIC lines are wired directly to codec, not PCH, so GPP_D17-20
  are set to NC
- Pads GPP_H0-H3 are configured for I2S2
- Pads GPP_H7-H9 are straps for board revision, so treated as GPI
- CPU_C10_GATE# is NC
- PWRBTN# does not need an internal pull-up
- GPP_C20-23 are configured for M.2 UART
- SATAXPCIE1/2 and EC SCI/SMI lines do not need internal pull ups
- GPP_C6/C7 set to I2C1 for future use
- GPP_E15 changed from SCI to SMI, edge triggered

Change-Id: If113cfeadf093e10dd84ab827ead594088f02ba1
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52389
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-18 20:39:23 +00:00
Matt DeVillier ab3fb6bba3 mb/purism/librem_14: Remove all PU/PD from NC GPIO pads
When a pad is configured as NC, it is set as a GPI with both
TX and RX disabled, and as the pad is internally disconnected,
no pull up or pull down is needed.

Change-Id: Id551b8f6f5b8c772e17670b8b728b5e890ef0b21
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52388
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-18 20:39:10 +00:00
Ivy Jian 49df72acfe mb/google/guybrush/var/guybrush: Add FPMCU configration
Enable CRFP in devicetree and configure GPIOs.

BUG=b:182201937
BRANCH=None
TEST=Boot into OS and confirm FPMCU is responding.

Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Change-Id: I7c56b0db193be6804d07c2f333445c2a1dbf9f59
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-18 20:38:40 +00:00
Marc Jones dc12daf277 src/drivers/ipmi: Add DEBUG_IPMI option
IPMI debug was extra spewy, so add a debug option as SPI and
other drivers have when they need to be debugged.

Change-Id: I788d67c242cac23bde9750aa3e95e3276c3f1fd7
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-18 20:37:10 +00:00