6 commits

Author	SHA1	Message	Date
Furquan Shaikh	05a6f29d32	soc/intel/skylake: Add support for GSPI controller ... Sky Lake PCH contains two GSPI controllers. Using the common GSPI controller driver implementation for Intel PCH, add support for GSPI controller buses on Sky Lake/Kaby Lake. BUG=b:35583330 Change-Id: I29b1d4d5a6ee4093f2596065ac375c06f17d33ac Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19099 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>	2017-04-06 00:45:36 +02:00
Furquan Shaikh	0de80da24c	soc/intel/skylake: Add support for SPI device ... Add a new PCI driver for SPI devices with supported PCI ids. Also, provide a translation table to convert struct device structure into SPI bus number. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: If860eb819f2ce5ae5443f808b356af57f86c52be Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18341 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>	2017-02-16 08:42:08 +01:00
Furquan Shaikh	dc1b294bfb	soc/intel/skylake: Add GSPI controller get_config support ... Provide implementation of get_config routine for GSPI controller on skylake platforms. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully. Change-Id: I5170076c15d72a7f29acd0989acef5b9149e2ba0 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18338 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>	2017-02-16 08:41:01 +01:00
Furquan Shaikh	42cfdf5184	soc/intel/skylake: Use the new SPI driver interface ... 1. Define controller for fast SPI. 2. Separate out functions that are specific to SPI and flash controller in different files. BUG=chrome-os-partner:59832 BRANCh=None TEST=Compiles successfully for chell and eve. Change-Id: I2fe0ef937297297339d4ea19dc37d3061caaa80c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17933 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>	2016-12-23 04:54:35 +01:00
Lee Leahy	1d14b3e926	soc/intel: Add Skylake SOC support ... Add the files to support the Skylake SOC. Matches chromium tree at 927026db BRANCH=none BUG=None TEST=Build and run on a Skylake platform Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>	2015-07-16 17:24:48 +02:00
Lee Leahy	b000513741	soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC ... Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>	2015-07-16 17:23:27 +02:00