Commit Graph

16 Commits

Author SHA1 Message Date
Kevin Chiu e1da21f687 util: Add DDR4 generic SPD for Micron MT40A1G16RC-062E-B 16Gb
Add SPD support for Micron DDR4 memory part MT40A1G16RC-062E-B 16Gb

BUG=b:184024142
TEST=none

Change-Id: I438310fb74d96953bc83374df3109e4c56192a5f
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-04-06 06:46:18 +00:00
Nick Vaccaro 96094b31e9 util: Add DDR4 generic SPD for H4AAG165WB-BCWE
Add SPD support for DDR4 memory part H4AAG165WB-BCWE.

BUG=b:181732562
TEST=none

Change-Id: I923fcbd08875a2a581fba4b1db00a4d1c1bb11cf
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51666
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-22 11:26:40 +00:00
Martin Roth f0a7e36527 util/spd_tools: Run go fmt on all .go files
This just reformats these files. go fmt should probably be
run on the check-in of every .go file.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I70ced115bad42d123474b18bbff2e4c0a16f3d88
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51019
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-27 09:37:34 +00:00
Nick Vaccaro 6745056a06 util: Add DDR4 generic SPD for H5ANAG6NCJR-XNC
Add SPD support for DDR4 memory part H5ANAG6NCJR-XNC.

BUG=b:161772961
TEST=none

Change-Id: I71e4de9a28f78bbf8c7de1fcafa3596276a5f2f9
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-12 08:38:27 +00:00
Rob Barnes 34cf7ccebc Revert "util/spd_tools: output binaries instead of hexdumps"
This reverts commit f23794cf04.

Reason for revert: This change breaks compatibility if the changes
in CB:44775 are not also included. CB:44775 is still under discussion,
so revert this change to make spd_tools usable again.

Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I5840a1b895dcbc8b91c76d8b60df2f95b93a4370
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44999
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-03 16:29:00 +00:00
Amanda Huang 873accd4a8 util: Add new memory part for zork boards
Add memory part H5ANAG6NDMR-XNC. Attributes are derived from data
sheets.

BUG=b:165611994
TEST=Compared generated SPD with data sheets and checked in SPD

Change-Id: Ifdcc7536441e9f0b94543c6f06fe466596f752dc
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-09-28 06:11:54 +00:00
Rob Barnes ad1da3a326 util/spd_tools: Support comments in mem_parts_used
Allow comments prefixed with '#' in mem_parts_used csv file.

BUG=None
TEST=Run gen_part_id with mem_parts_used file containing comments

Change-Id: Ia9e274d45aa06dea7a3a5f8cd1c8ee2b23398876
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-09 10:46:03 +00:00
Michael Niewöhner f23794cf04 util/spd_tools: output binaries instead of hexdumps
Instead of generating hexdumps, output binary SPD files since we plan to
convert all hex SPD files to binary. Also adjust the file extension
where needed.

Test: compared generated binaries with converted binaries from hex files

Change-Id: Ie99d108ca90758d09dbefad20fe6c9f7fc263ef1
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-08 05:46:41 +00:00
Rob Barnes 8283ae6bab util: Add memory parts needed by zork boards
Add memory parts needed by zork boards. Attributes are derived from data
sheets.

BUG=b:162939176
TEST=Compared generated SPDs with data sheets and checked in SPDs

Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I67f205f9af24bbc5c12656be1f363a15fe975955
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44447
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28 14:29:44 +00:00
Nick Vaccaro 913ea9278f util/gen_spd: translate DeviceBusWidth to die bus width
If a memory part is a x16 part that has two dies and only a single
rank, then the x16 describes the part width (since this solution will
need to be a stacked solution) and as such, we must translate the
DeviceBusWidth to the "die bus width" instead.

Change DeviceBusWidth variable name to PackageBusWidth to be more
descriptive

BUG=b:166645306, b:160157545
TEST=run gen_spd and verify that spds for parts matching description
above changed appropriately.

Change-Id: Ia6f3ca109d344b7a015da28125a94ce10d2bdfb8
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-28 14:20:30 +00:00
Rob Barnes a662648a7f util: Add support to spd_tools for fixed id
For boards that have already assigned memory ids, there needs to be a
way to fix parts to a specific id. After assigning all the fixed ids the
tool still attempts to minimize the SPDs entries. Since a fixed ID could
be anywhere, gaps can be created in the list. So an empty SPD entry is
created to fill the gaps in the list until they are used.

BUG=b:162939176
TEST=Generate various outputs

Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I1f8ea1ff4f33a97ab28ba94896a1054e89189576
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-08-28 04:36:55 +00:00
Nick Vaccaro 48fc1640a8 util: volteer/dedede: move generic SPDs to common location
Now that generic SPD files have the memory type prepended to the
filename, they can be stored in the same location.  This CL moves
the generic SPDs to the new location.

Change the ddr4 gen_part_id.go and gen_spd.go tools to use
"ddr4_spd_manifest.generated" instead of "spd_manifest.generated".

Change the lpddr4x gen_part_id.go and gen_spd.go tools to use
"lp4x_spd_manifest.generated" instead of "spd_manifest.generated".

Move TGL DDR4 and LPDDR4x generic SPDs into a common location.

Move JSL DDR4 and LPDDR4x generic SPDs into a common location.

Change the volteer/spd/Makefile.inc to use the new path for the spds.

Change the dedede/spd/Makefile.inc to use the new path for the spds.

BUG=b:165854055
TEST="emerge-volteer coreboot" and verify all variants build correctly.

Change-Id: I83b088cb718d15ffd3012c84a12b5231ae84a3e4
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44648
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28 04:35:56 +00:00
Rob Barnes c19140b49f util: Add check for duplicate entries in mem parts json
Check for duplicate entries in mem parts json file.

BUG=b:162939176
TEST=Verified that tool throws error when there is a duplicate.

Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I7c638c7938958727cfc832e7b4556acbc04b0ca4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44478
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-27 22:39:32 +00:00
Rob Barnes 8cc80d5e50 util: Add Picasso and Pollock platforms to spd_tools
PCO = Picasso
PLK = Pollock

BUG=b:162939176

Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I43b74f68871062112f53fbbef8a170db53734b3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44477
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-27 21:41:30 +00:00
Rob Barnes a2e431331c util/spd_tools: Support comments in json
Allow comments in json file for better documentation. Comments must be
on seperate line.

BUG=none
TEST=Injest global_ddr4_mem_parts.json.txt with comments

Change-Id: I51295408d4f916708e4ed5bc42d5468ccdc68a6b
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-27 21:41:18 +00:00
Rob Barnes 196e9c0021 util/spd_tools: Remove intel subfolder
Move ddr4 and lp4x to spd_tools root folder. The tool now applies to non
intel platforms.

BUG=b:162939176
TEST=Run tool

Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I0941ea036d760ee27eb34f259f4506a4b7584bee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44844
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-27 20:14:34 +00:00