Change allows to override default bootblock_mainboard_init() with
mainboard-specific code.
If the default bootblock_mainboard_init() handler is replaced, with
one from file BOOTBLOCK_MAINBOARD_INIT, one needs to take care the
replacement calls all the necessary bootblock_x_init() functions.
Change-Id: Ie8c667cdba7cafe9ed2d4b19ab2bd21d941ad4ca
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1845
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Makes it a bit easier to implement mainboard-specific behaviour
while executing the bootblock.
Change-Id: I04e87f89efb4fad1c0e20b62ea6a50329a286205
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1844
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This is an initial re-factoring of CBFS code to enable multiple
architectures. To achieve a clean solution, an additional field
describing the architecture has to be added to the master header.
Hence we also increase the version number in the master header.
Change-Id: Icda681673221f8c27efbc46f16c2c5682b16a265
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/1944
Tested-by: build bot (Jenkins)
Not sure why this never triggered an error before.
Change-Id: I85d8b3b862492df04163a5f751c7ea4288406860
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1946
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This adds a dummy config for ARMV7 for developing various
follow-up patches which rely on ARCH_ARMV7.
Change-Id: Id913054d916f41607d10ebc02aaf74082e14b554
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/1939
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Create a new directory in drivers for power controllers.
Add the MAXIM MAX77686 power control support.
Accessing this controller requires I2C support.
Note that this will not build until the I2C usage is changed for
coreboot. I'm putting it in mainly because we need it soon
and I want to see if the new directory is acceptable.
Change-Id: I6c2a6d2165f33b41d2c8e4813222b21d2385e879
Signed-off-by: David Hendricks <dhendrix@chromium.org>
SIgned-off-by: Hung-Te Lin <hungte@chromium.org>
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/1938
Tested-by: build bot (Jenkins)
This provides weak empty declaration for mainboard_ops.
The struct chip_operations is not defined for __PRE_RAM__ so
the declaration is also moved upwards in the output.
Change-Id: I101f0b8b9f0a55fb51a7c6475d53cc588c84026d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1931
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
With these changes we have a mostly compiling target.
I'm still removing and pruning .h files, but hopefully later today I'll do
the last few .h commits and move on to .c
Change-Id: Ia82d787496184e028f37d7b67336d61fda75aa94
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/1937
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
As we move to supporting other systems we need to get rid of assembly
where we can. The log2 function in src/lib is identical to the assembly
one (tested for all 32-bit signed integers :-) and takes about 10 ns
to run as opposed to 5ns for the non-portable assembly version. While speed
is good, I think we can spare the 15 ns or so we add to boot time
by using the C version only.
Change-Id: Icafa565eae282c85fa5fc01b3bd1f110cd9aaa91
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/1928
Tested-by: build bot (Jenkins)
Change-Id: I48497adc29a1b8ca11d1e0a5d879cab5b6b55dcd
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/1926
Tested-by: build bot (Jenkins)
Per a conversation with Stefan, these chip-dependent files are moved
to the src tree, in the manner of other chips (north and southbridge).
Change-Id: I12645ba05eb241eda200ed06cb633541a6a98119
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Reviewed-on: http://review.coreboot.org/1925
Tested-by: build bot (Jenkins)
This gets rid of the somewhat unstructured placement of AMD's
sysinfo structure in CAR.
We used to carve out some CAR space using a Kconfig variable,
and then put sysinfo there manually (by "virtue" of pointer magic).
Now it's a variable with the CAR_GLOBAL qualifier, and build
system magic.
For this, the following steps were done (but must happen together
since the intermediates won't build):
- Add new CAR_GLOBAL sysinfo_car
- point all sysinfo pointers to sysinfo_car instead of GLOBAL_VAR
- remove DCACHE_RAM_GLOBAL_VAR_SIZE
- from CAR setup (no need to reserve the space)
- commented out code (that was commented out for years)
- only copy sizeof(sysinfo) into RAM after ram init, where
before it copied the whole GLOBAL_VAR area.
- from Kconfig
Change-Id: I3cbcccd883ca6751326c8e32afde2eb0c91229ed
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1887
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Marc Jones <marcj303@gmail.com>
This broke because those components were not yet
committed when the patch to drop the driver class
was made.
Change-Id: I29948223503a6c4b196eafa169c064cd26da1be1
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1934
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
- Optionally override FSB clock detection in generic
LAPIC code with constant value.
- Override on AMD Model fxx, 10xxx, agesa CPUs with 200MHz
- compile LAPIC code for romstage, too
- Remove #include ".../apic_timer.c" in AMD based mainboards
- Remove custom udelay implementation from intel northbridges' romstages
Future work:
- remove the compile time special case
(requires some cpuid based switching)
- drop northbridge udelay implementations (i945, i5000) if
not required anymore (eg. can SMM use the LAPIC timer?)
Change-Id: I25bacaa2163f5e96ab7f3eaf1994ab6899eff054
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1618
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
When dropping ramstage.a, unused functions with unresolved
symbols are not silently dropped anymore. This makes the
tim5690 compilation fail.
This fix makes sure we don't compile in the int15 handler code
when we don't set CONFIG_VGA_ROM_RUN
Change-Id: If6872c983d9fd811eb33259421f94b551f3b9b34
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1929
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
Change-Id: Ib4401897570f9e4d31c18d05144b5deb6f4523bc
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/1873
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Marc Jones <marcj303@gmail.com>
When dropping ramstage.a duplicate symbols in ramstage
will start breaking the build. Hence drop all the duplicate
functions implemented by mainboards that have those functions
in generic or component code already.
Change-Id: I5cf8245c67b6f0f348388db54256d28f47017a61
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1865
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
c_start.o has a special case in the build system, which we can
eliminate, somewhat simplifying the build.
To ensure that the entry point is at the beginning, introduce a
new section .textfirst that is placed appropriately. In principle
the ENTRY() definition in the linker script should be enough, but
better be safe.
Change-Id: I9737f7f5731e12ceb2119eb432b0e09832bc53fa
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1909
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The use of ramstage.a required the build system to handle some
object files in a special way, which were put in the drivers
class.
These object files didn't provide any symbols that were used
directly (but only via linker magic), and so the linker never
considered them for inclusion.
With ramstage.a gone, we can drop this special class, too.
Change-Id: I6f1369e08d7d12266b506a5597c3a139c5c41a55
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1872
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
ramstage.a has two issues:
1. duplicate source filenames don't survive the ar(1)
treatment properly (so files aren't considered)
2. ld doesn't resolve symbols if it isn't forced to, in
particular no overrides of weak symbols
Downside: The resulting binaries get slightly larger.
Link time optimizations should fix that, as would tighter
rules in the build system (to not compile unused code in
the first place).
Change-Id: Iaae771ec8f92b42069237acd3b79c14e5bf9c03d
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1566
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
sconfig creates empty defaults for all chip_ops, which can be overridden
by drivers simply by providing a concrete implementation.
Change-Id: Ib37515f0b0747bdbf4da780d28690a1e719944b2
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1567
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The calculation of COMB's irq reading was wrong by the 4-bit shift.
Also, the asl compiler warned about the splitting in lo/hi bytes which
seems unnecessary.
Change-Id: Ia5101d5a19f68c2da827d7e37a18922f959604c7
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1923
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Forgot to update the rk9 for the unified VGABIOS handling.
This applies to rk9 what is done for other boards in commits
3c84261e84d5d340695b
Change-Id: I892b7d81927e277778c1c5251d27416fa79c9868
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1924
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
For SST chips, the Write-Status-Register instruction must be
executed immediately after the execution of the
Enable-Write-Status-Register instruction, instead of Write-Enable.
Change-Id: I4b3473cd671829def3bd1641ececcf8d9dad4a56
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1919
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Roda RK9 is a notebook based on the GM45/ICH9 platform using DDR3 memory.
http://roda-computer.com/products/notebooks/rk9/
Tested with various Linux versions, known to work:
- 2x4GB RAM
- IGD
- HD Audio
- UHCI, EHCI
- AHCI
- NIC
- PCI
- PS/2 keyboard
- serial console
- ACPI lid switch
- ACPI battery/AC events
- power off, reboot
Change-Id: I7299dccbff2eea3544363fdd4f49f05aa3dae7bc
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1691
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Add support for ICH9 southbridge
Change-Id: I70612431101bf48d9dcc96ee1b37d257c9ad2ee2
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1690
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
The code supports DDR3 boards only. RAM init for DDR2 is sufficiently
different that it requires separate code, and we have no boards to
test that.
Change-Id: I9076546faf8a2033c89eb95f5eec524439ab9fe1
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1689
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add an init() function to the chip_operations which will be called
before bus enumeration. This allows to disable unused devices before
they get enumerated.
Change-Id: I63dd9cbfc7b5995ccafb7bf7a81dc71fc67906a0
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1623
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This will omit the mc1468181rtc header if it is not needed. Currently
it contains a lot of inlined functions which depend on architecture-
specific IO.
Change-Id: I4ef1bc1362c159e0c780c3eade01af04f029f949
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/1916
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
This adds more configurability to POST codes. The current assumption
is that POST codes should be written to an IO port (e.g. LPC) if POST
codes are enabled. This changes the assumption so that POST codes can
be written to the serial console without being written to an IO port.
This enables POST codes by default using "default y" to avoid
changing current behavior.
Change-Id: I3db91c358ccb1557096983c4d07f70b2e872c4b3
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/1685
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Some boards have two instances of the int15 handler that supports
the onboard VGA BIOS, for YABEL and realmode.
These are now similar enough that they can be deduplicated.
Due to minor differences this requires manual effort.
Change-Id: I03ae314cb90dd65d96591ce448504aa961cbeb88
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1893
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Makes it more similar to what realmode looks like.
Change-Id: I4407431f2d979c43dd186114d67ed11845907afe
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1892
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
By using the (global) register file as defined by x86emu,
we can use the same register access for YABEL and realmode
interrupt handlers.
- the x86 realmode interrupt handlers changed in signature
- to access registers, use X86_$REGNAME now (eg. X86_EAX)
- x86_exception_handler still uses struct eregs *regs to
avoid spilling the x86emu register file stuff everywhere
Coccinelle script that handled most of this commit:
@ inthandler @
identifier FUNC, regs;
@@
int FUNC(
-struct eregs *regs
+void
)
{ ... }
@ depends on inthandler @
identifier regs;
@@
-regs->eax
+X86_EAX
@ depends on inthandler @
identifier regs;
@@
-regs->ebx
+X86_EBX
@ depends on inthandler @
identifier regs;
@@
-regs->ecx
+X86_ECX
@ depends on inthandler @
identifier regs;
@@
-regs->edx
+X86_EDX
@ depends on inthandler @
identifier regs;
@@
-regs->esi
+X86_ESI
@ depends on inthandler @
identifier regs;
@@
-regs->edi
+X86_EDI
@ depends on inthandler @
identifier regs;
@@
-regs->eflags
+X86_EFLAGS
@ depends on inthandler @
identifier regs;
@@
-regs->vector
+M.x86.intno
Change-Id: I60cc2c36646fe4b7f97457b1e297e3df086daa36
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1891
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
realmode int handlers must return the same codes as the YABEL
int handlers now: 1 for "interrupt handled", 0 for "not handled"
(ie. error).
Change-Id: Idc01cf64e2c97150fc4643671a0bc4cca2ae6668
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1890
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
It's really a feature in parallel to YABEL/x86emu. Reflect this in
the directory structure.
Change-Id: Ie88e4fa6bfef13d23c55b2db3faacbd90f8cc30b
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1889
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: I4128af7912bec090bbd48acc1b20d0452e7a4a28
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/1876
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
e.g.
-#if CONFIG_LOGICAL_CPUS == 1
+#if CONFIG_LOGICAL_CPUS
This will make it easier to switch over to use the config_enabled()
macro later on.
Change-Id: I0bcf223669318a7b1105534087c7675a74c1dd8a
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1874
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This unused code was not silently dropped as before.
Change-Id: Ic76c58e233869a60c3a8a27c2efc2182b3a4442d
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1863
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The Agesa wrapper and UDELAY_TIMER2 define their own timer functions,
so don't shove in UDELAY_IO
Change-Id: Ibe3345e825e0c074d5f531dba1198cd6e7b0a42d
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1864
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This code used a special case for checksum calculation to
prevent the century byte from messing things up, since
writes "sometimes" didn't happen.
That should be stable now, so the special case isn't necessary.
Downside: On century rollovers (ie. 1999-12-31, 2099-12-31)
CMOS will be reset to the defaults.
Change-Id: Ibe589a1ec953b7b3ba39be30cebd9fc2b27326ae
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1870
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This ensures that there's only one disable/enable cycle for
the entire rewrite instead for every single byte.
Change-Id: Ic06e6dcb08976d158ff784660838c0fbad875176
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1869
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
In principle this isn't necessary. However there's a byte (or several)
outside the first 14 bytes that are part of the RTC, and require
locking (century/altCentury).
Since their location is mostly unknown, guard writes properly.
Change-Id: I847cd4efa92722e8504d29feaf7dbfa5c5244b4e
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1868
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
intel_irq_routing_table is a local structure that should not be used
globally, because it might not be there on all mainboards.
Instead, the API has to be corrected to allow passing a PIRQ table in
where needed.
Change-Id: Icf08928b67727a366639b648bf6aac8e1a87e765
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1862
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Some boards selected GENERATE_ instead of HAVE_
Change-Id: I450c22d7b044f0c88c21692246d452d516a68a83
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1841
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Kyösti Mälkki