Commit graph

9 commits

Author SHA1 Message Date
Nitheesh Sekar
f371b051b0 qcs405: Update bootblock size
Increase the size of bootblock from 96K to 128K.

Change-Id: Ifc6e7239ed2978a8490fa229945ebd5ed9182298
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33159
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-21 08:48:42 +00:00
Nitheesh Sekar
3f89da8d65 qcs405: Add PRESERVE flag for RO_VPD
Add PRESERVE flag to preserve the VPD data.

Change-Id: I78ab4de31030465345c5ae58813bfed5e27494fb
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33020
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06 19:55:43 +00:00
Nitheesh Sekar
a2c219a91d qcs405: Enable SPI-NOR
Enable support for Gigadevice spi-nor flash.

Change-Id: I340eb3bf77b25fe3502d4b29ef4bf7c06b282c02
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-06-02 19:52:37 +00:00
Patrick Georgi
c82acf5931 qualcomm/qcs405: enable SPI bus 4 for TPM
Change-Id: Ic282daf10dad42bc4513cc55f15ce80a4bd316a5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Signed-off-by: Prudhvi Yarlagadda <pyarlaga@codeaurora.org>
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-02 19:51:50 +00:00
Elyes HAOUAS
9d6f645908 mainboard: Remove unused include <timestamp.h>
Change-Id: Id05fc39c0c0d0560e34e55f793060d29df82d026
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2019-05-13 09:13:19 +00:00
Nitheesh Sekar
69cc491c3f Mistral: Enable USB in romstage
Enable USB support for mistral in romstage.

TEST=build & run

Change-Id: I5c2bbe16aa3601e014a2b77d192565402ed23794
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-28 10:36:29 +00:00
santhosh hassan
0eb4db185c google/mistral: Implement board reset
Implement reset using PSHOLD.

Change-Id: I472bf73cc7b227187b284a3730ec5dea5373695c
Signed-off-by: Santhosh Hassan <sahassan@google.com>
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31827
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-20 13:54:37 +00:00
Nitheesh Sekar
0dd80aab25 mistral: qcs405: copy calibration data to CBMEM
This patch adds support to copy the wifi calibration
data to CBMEM so that the depthcharge can use it to
populate the data into wifi dt node.

Change-Id: Ia8184e48a7176bb3b52e4d43866b7d065952c13e
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-20 13:54:02 +00:00
Nitheesh Sekar
918fc00fb4 mainboard/google/mistral: Add support for Mistral
Adding a new board variant 'Mistral' based on qcs405 soc.

TEST=build

Change-Id: I7ecfad68bb50f42acf36f51bc3433add56597c3d
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-18 18:17:12 +00:00