Commit Graph

84 Commits

Author SHA1 Message Date
Alexander Goncharov 893c3ae892 tree: Drop repeated words
Found-by: linter
Change-Id: I7c6d0887a45fdb4b6de294770a7fdd5545a9479b
Signed-off-by: Alexander Goncharov <chat@joursoir.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72795
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-07 04:37:31 +00:00
Elyes Haouas f82e68c900 spd.h: Move enum ddr3_module_type to ddr3.h
Move specific enum ddr3_module_type to <device/dram/ddr3.h>.

Change-Id: I8fd7892dda26158a5bdd6cd4972c7859a252153e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71547
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-04 12:39:32 +00:00
Elyes Haouas 5a04746714 spd.h: Move enum ddr2_module_type to ddr2.h
Move specific enum ddr2_module_type to <device/dram/ddr2.h>.

Change-Id: I748658f9b349bff9b1ebe2c0a6acf71bf2a221ce
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71546
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-01-04 07:22:58 +00:00
Julius Werner 9a9b2778a1 coreboot_tables: Make existing alignment conventions more explicit
There seem to be some recurring vague concerns about the alignment of
coreboot table entries. While the existing implementation has been
producing tables with a well-defined alignment (4 bytes) for a long
time, the code doesn't always make it very clear. This patch adds an
explicit constant to codify that alignment, assertions to check it after
each entry, and adds explicit padding to the few entry structures that
were relying on compiler padding to return a correct sizeof() value.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Iaeef29ef255047a855066469e03b5481812e5975
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70158
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peter Stuge <peter@stuge.se>
2022-12-22 15:34:28 +00:00
Elyes Haouas 799c321914 cbmem_top_chipset: Change the return value to uintptr_t
Get rid of a lot of casts.

Change-Id: I93645ef5dd270905ce421e68e342aff4c331eae6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2022-11-18 16:00:45 +00:00
Arthur Heymans 9948c521a6 lib/coreboot_table: Simplify API to set up lb_serial
Instead of having callbacks into serial console code to set up the
coreboot table have the coreboot table code call IP specific code to get
serial information. This makes it easier to reuse the information as the
return value can be used in a different context (e.g. when filling in a
FDT).

This also removes boilerplate code to set up lb_console entries by
setting entry based on the type in struct lb_uart.

Change-Id: I6c08a88fb5fc035eb28d0becf19471c709c8043d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2022-11-04 19:17:13 +00:00
Eric Lai 01590227f2 test/lib: Add non-existent DIMMs test case in spd_cache-test
Add non-existent DIMMs test case in spd_cache-test.

BUG=b:213964936
TEST=make unit-tests PASSED

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I3c8aa92ee0cfd5908399f4bbd305f8f306571d40
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2022-11-03 13:00:15 +00:00
Arthur Heymans ea1e36694d coreboot_tables: Drop uart PCI addr
Only edk2 used this to fill in a different struct but even there the
entries go unused, so removing this struct element from coreboot has
no side effects.

Change-Id: Iadd2678c4e01d30471eac43017392d256adda341
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-10-26 14:12:06 +00:00
Elyes Haouas f25c11236a tests/lib/coreboot_table-test.c: Use ALIGN_UP macro
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ie0d4788c0a4ffee2f16bcf05e3454dbaeaa1606b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2022-09-12 15:31:37 +00:00
Nico Huber 526c64249a allocator_v4: Introduce RESOURCE_ALLOCATION_TOP_DOWN
Add option to resource allocator v4 that restores the top-down
allocation approach at the domain level.

This makes it easier to handle 64-bit resources natively. With
the top-down approach, resources that can be placed either above
or below 4G would be placed above, to save precious space below
the 4G boundary.

Change-Id: Iaf463d3e6b37d52e46761d8e210034fded58a8a4
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41957
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-09-04 16:35:22 +00:00
Julius Werner d96ca24652 cbfs/vboot: Adapt to new vb2_digest API
CL:3825558 changes all vb2_digest and vb2_hash functions to take a new
hwcrypto_allowed argument, to potentially let them try to call the
vb2ex_hwcrypto API for hash calculation. This change will open hardware
crypto acceleration up to all hash calculations in coreboot (most
notably CBFS verification). As part of this change, the
vb2_digest_buffer() function has been removed, so replace existing
instances in coreboot with the newer vb2_hash_calculate() API.

Due to the circular dependency of these changes with vboot, this patch
also needs to update the vboot submodule:

Updating from commit id 18cb85b5:
    2load_kernel.c: Expose load kernel as vb2_api

to commit id b827ddb9:
    tests: Ensure auxfw sync runs after EC sync

This brings in 15 new commits.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I287d8dac3c49ad7ea3e18a015874ce8d610ec67e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2022-09-02 23:51:29 +00:00
Nico Huber c0e3004af0 tests/memrange-test: Correct final end test in test_memrange_steal()
If an inserted region's base wasn't aligned, the resulting range should
still cover the original end (original region's base + size) and not the
aligned-down base + size.

Change-Id: I8f1c9456d6dbab4fa868de5c93fa3656397e54c1
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66607
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-26 17:35:54 +00:00
Nico Huber 875f7315f3 tests/memrange-test: Correct commentary on test_memrange_steal()
Currently, memranges_steal() steals at the lowest possible address.
This is actually reflected by the test code that checks if the *base*
of the READONLY_TAG range changes. Furthermore, the test ends with the
memranges restored, so revise the comment on the final state.

Change-Id: Idef71ce464280c6805145f229de9e8913ba850bc
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66606
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Jan Dabros <jsd@semihalf.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-26 17:29:08 +00:00
Shuo Liu d914292142 tests/lib: Do not pick up unassigned resources
Unassigned tag is defined to emulate an unmapped PCI BAR resource.
This resource is not mapped into host physical address and hence
should not be picked up by memranges_add_resources().

Change-Id: If7a5c437d486b80d798496b985efd80526f13c63
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Dabros <jsd@semihalf.com>
2022-08-13 16:40:26 +00:00
Shuo Liu 85894aa5bc tests/lib: Set IORESOURCE_ASSIGNED for bootmem-test and memrange-test
IORESOURCE_ASSIGNED is used to indicate the resource is actually mapped
host physical address space. E.g. PCI BAR resources not mapped are
not regarded as assigned.

In src/include/device/device.h, standard macros, e.g. ram_resource,
mmio_resource, io_resource, et al, are all following the usage above.
This patch updates the bootmem-test and memrange-test to follow the
usage as well.

Change-Id: Ifc19302482038267cef01321a46a72d90ca76d35
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66450
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Jan Dabros <jsd@semihalf.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-13 16:38:41 +00:00
Eric Lai 3067701108 lib: Check for non-existent DIMMs in check_if_dimm_changed
Treat dimm addr_map 0 non-existent. addr_map default is 0, we don't set
it if Hw is not present. Also change the test case default to avoid 0.
SODIMM SMbus address 0x50 to 0x53 is commonly used.

BUG=b:213964936
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage
The MRC training does not be performed again after rebooting.

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I2ada0109eb0805174cb85d4ce373e2a3ab7dbcac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-20 06:57:21 +00:00
Jakub Czapiga c91b55a201 tests: update CMocka to stable-1.1
CMocka stable-1.1 has some convenience bugfixes like vprint buffer
increase or leftover values log fix (funtion names display correctly
now.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I20ebd15324a21c17cccd2976ae9c3f86b040426d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63636
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-04-19 13:00:36 +00:00
Jianjun Wang b2537bdad5 coreboot_tables: Replace 'struct lb_uint64' with lb_uint64_t
Replace 'struct lb_uint64' with 'typedef __aligned(4) uint64_t
lb_uint64_t', and remove unpack_lb64/pack_lb64 functions since it's no
longer needed.

Also replace 'struct cbuint64' with 'cb_uint64_t' and remove
'cb_unpack64' in libpayload for compatible with lb_uint64_t.

Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: If6b037e4403a8000625f4a5fb8d20311fe76200a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-04-14 22:27:50 +00:00
Paul Menzel 77b1ff0f9d tests/lib: Add space before single line comment termination
Change-Id: I9321391cc06afddff94fbba79f93851b553c74b1
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2022-03-27 15:33:39 +00:00
Arthur Heymans 2e7e2d978b coreboot_tables.c: Expose the ACPI RSDP
The ACPI RSDP can only be found in:
- legacy BIOS region
- via UEFI service

On some systems like ARM that legacy BIOS region is not an option, so
to avoid needing UEFI it makes sense to expose the RSDP via a coreboot
table entry.

This also adds the respective unit test.

Change-Id: I591312a2c48f0cbbb03b2787e4b365e9c932afff
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62573
Reviewed-by: Lance Zhao
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-09 14:21:01 +00:00
Julius Werner 69cc557cfb commonlib/bsd: Remove cb_err_t
cb_err_t was meant to be used in place of `enum cb_err` in all
situations, but the choice to use a typedef here seems to be
controversial. We should not be arbitrarily using two different
identifiers for the same thing across the codebase, so since there are
no use cases for serializing enum cb_err at the moment (which would be
the primary reason to typedef a fixed-width integer instead), remove
cb_err_t again for now.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Iaec36210d129db26d51f0a105d3de070c03b686b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-09 02:18:21 +00:00
Jakub Czapiga ad6157ebdf timestamps: Rename timestamps to make names more consistent
This patch aims to make timestamps more consistent in naming,
to follow one pattern. Until now there were many naming patterns:
- TS_START_*/TS_END_*
- TS_BEFORE_*/TS_AFTER_*
- TS_*_START/TS_*_END
This change also aims to indicate, that these timestamps can be used
to create time-ranges, e.g. from TS_BOOTBLOCK_START to TS_BOOTBLOCK_END.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I533e32392224d9b67c37e6a67987b09bf1cf51c6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-08 16:06:33 +00:00
Jakub Czapiga c08b6a7037 tests: Fix tests code and comments style
This patch applies clang-format settings to most of tests files. Some
files were fixed "by-hand" to exclude some lines, which whould be less
readable after automatic style fixing.
Moreover, some comments (mostly in tests/lib/edid-test.c) were adjusted
to match coreboot coding style guidelines.

Change-Id: I69f25a7b6d8265800c731754e2fbb2255f482134
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2022-01-14 14:29:29 +00:00
Jakub Czapiga 727a84b9a7 tests: Move EDID test header to include/tests/lib
Move header to path with all other test headers to make include paths
unambigous.

Change-Id: Ie2dbb055df658272424df95f58d84caaeba3fc8f
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60969
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-01-12 23:33:05 +00:00
Jakub Czapiga 19ad39b7f2 tests/lib/lzma-test: Fix uninitialized array error
Change-Id: I5b10eef3dd82068f97d4d875f3da813a5aca07a7
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reported-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60112
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-15 17:07:27 +00:00
Jianjun Wang 8bb59ca2fa lib: Add __fls() (Find Last Set)
Implement __fls() as an alias for log2(), and remove the duplicate
definitions in commonlib/storage/sdhci.c.

Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: Ib458abfec7e03b2979569a8440a6e69b0285ac32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-12-13 02:57:07 +00:00
Yu-Ping Wu 00c834dc26 lib: Fix log2_ceil() for 0xffffffff
Current log2_ceil(x) is defined as log2(x * 2 - 1). When x is larger
than (1 << 31), (x * 2 - 1) won't fit in u32, leading to incorrect
result. Therefore, correct it as (log2(x - 1) + 1). Also add unit tests
for inline functions in lib.h.

BUG=none
TEST=make tests/lib/lib-test
BRANCH=none

Change-Id: If868f793b909a6ad7fc48a7affac15e2c714fa2e
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-12-08 00:51:43 +00:00
Julius Werner 9f37647b04 cbfs: Remove deprecated APIs
This patch removes all remaining pieces of the old CBFS API, now that
the last straggling use cases of it have been ported to the new one
(meaning cbfs_map()/cbfs_load()/etc... see CB:39304 and CB:38421).

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I1cec0ca2d9d311626a087318d1d78163243bfc3c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-12-06 12:36:45 +00:00
Jakub Czapiga ea619425ee commonlib: Move commonlib/cbmem_id.h to commonlib/bsd/
Libpayload requires cbmem_id.h file to support extracting values from
CBMEM IMD entries of coreboot tables. Libpayload use BSD-3-Clause
license, and all of its files used to compile a static library have to
use it too.

Change-Id: I97c080e34ebdbcdf14fe3a3c9515b1dea8ede179
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
2021-11-30 17:23:37 +00:00
Subrata Banik 6de8b42482 arch/x86: Refactor the SMBIOS type 17 write function
List of changes:
1. Create Module Type macros as per Memory Type
(i.e. DDR2/DDR3/DDR4/DDR5/LPDDR4/LPDDR5) and fix compilation
issue due to renaming of existing macros due to scoping the Memory
Type.
2. Use dedicated Memory Type and Module type for `Form Factor`
and `TypeDetail` conversion using `get_spd_info()` function.
3. Create a new API (convert_form_factor_to_module_type()) for
`Form Factor` to 'Module type' conversion as per `Memory Type`.
4. Add new argument as `Memory Type` to
smbios_form_factor_to_spd_mod_type() so that it can internally
call convert_form_factor_to_module_type() for `Module Type`
conversion.
5. Update `test_smbios_form_factor_to_spd_mod_type()` to
accommodate different memory types.
6. Skip fixed module type to form factor conversion using DDR2 SPD4
specification (inside dimm_info_fill()).

Refer to datasheet SPD4.1.2.M-1 for LPDDRx and SPD4.1.2.L-3 for DDRx.

BUG=b:194659789
TEST=Refer to dmidecode -t 17 output as below:
Without this code change:

Handle 0x0012, DMI type 17, 40 bytes
Memory Device
        Array Handle: 0x000A
        Error Information Handle: Not Provided
        Total Width: 16 bits
        Data Width: 16 bits
        Size: 2048 MB
        Form Factor: Unknown
        ....

With this code change:

Handle 0x0012, DMI type 17, 40 bytes
Memory Device
        Array Handle: 0x000A
        Error Information Handle: Not Provided
        Total Width: 16 bits
        Data Width: 16 bits
        Size: 2048 MB
        Form Factor: Row Of Chips
        ....

Change-Id: Ia337ac8f50b61ae78d86a07c7a86aa9c248bad50
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-11 09:10:10 +00:00
Raul E Rangel 4c8c8442ab lib/list: Add list_append
This method will add a node to the end of the list.

BUG=b:179699789
TEST=Boot guybrush to the OS

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I1792e40f789e3ef16ceca65ce4cae946e08583d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-03 08:29:16 +00:00
Subrata Banik 3306f37fd6 lib: Add new argument as `ddr_type` to smbios_bus_width_to_spd_width()
Add DDR5 and LPDDR5 memory type checks while calculating bus width
extension (in bits).

Additionally, update all caller functions of
smbios_bus_width_to_spd_width() to pass `MemoryType` as argument.

Update `test_smbios_bus_width_to_spd_width()` to accommodate
different memory types.

Create new macro to fix incorrect bus width reporting
on platform with DDR5 and LPDDR5 memory.

With this code changes, on DDR5 system with 2 Ch per DIMM, 32 bit
primary bus width per Ch showed the Total width as:

Handle 0x000F, DMI type 17, 40 bytes
Memory Device
	Array Handle: 0x0009
	Error Information Handle: Not Provided
	Total Width: 80 bits
	Data Width: 64 bits
	Size: 16 GB
	...

BUG=b:194659789
Tested=On Alder Lake DDR5 RVP, SMBIOS type 17 shows expected `Total Width`.

Change-Id: I79ec64c9d522a34cb44b3f575725571823048380
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-11-02 08:13:25 +00:00
Jakub Czapiga c1e4c5aaa5 tests: Add lib/lzma-test test case
Files used by this test are in: tests/data/lib/lzma-test/
file.bin - files with uncompressed data
file.lzma.bin - files with LZMA-compressed data from file.bin

How to prepare compressed file:
  util/cbfs-compression-tool compress file.bin /tmp/file.lzma.bin lzma
  dd if=/tmp/file.lzma.bin of=file.lzma.bin skip=8 ibs=1

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Id75e0b41991382d4c391b031862106de58eacdf7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-10-14 13:13:07 +00:00
Jakub Czapiga b20aa094cc tests: Add lib/cbfs-lookup-test test case
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I2ebebba1468c19661741de8a8456605b1c5f56b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-09-14 23:35:38 +00:00
Jakub Czapiga 6f3fd6358f tests: Add lib/cbfs-verification-test test case
This commit adds test case for lib/cbfs verification mechanisms.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I1d8cbb1c2d0a9db3236de065428b70a9c2a66330
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56601
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-02 00:31:02 +00:00
Jakub Czapiga 7c6081e02b tests: Improve test output readability
When running multiple tests, e.g. by using unit-tests target, it is hard
to differentiate, which output comes from which file and/or
configuration. This patch makes the output easier to analyze and
understand by using new wrapper macro cb_run_group_tests(). This macro
uses __TEST_NAME__ value (containing test path and Makefile test name)
as a group name when calling cmocka group runner.

Example:
 Test path: tests/lib/
 Makefile test name: cbmem_stage_cache-test
 Test group array name: tests
 Result: tests/lib/cbmem_stage_cache-test(tests)

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I4fd936d00d77cbe2637b857ba03b4a208428ea0d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-09-01 19:38:09 +00:00
Jakub Czapiga d0bd012b5e tests/Makefile.inc: Add missing include paths to TEST_CFLAGS
Add missing paths to common tests cflags and remove these paths from
individual tests configuration.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I13cb336195bfb06b861d7f403822f06bec8a40aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-08-13 18:05:55 +00:00
Jakub Czapiga ca3aa52cf8 tests: Add lib/libgcc-test test case
Add tests for src/lib/libgcc.c __clzsi2() implementation. Unlike GCC
implementation, coreboot one can handle zero input.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I3f46071d0921e8c5edc5df3c296d11c77de01c88
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-07-26 07:32:43 +00:00
Patrick Georgi ce55ca2fca tests: Rework mocking facility
Using the linker's --wrap feature has the downside that it only covers
references across object files: If foo.c defines a() and b(), with b
calling a, --wrap=a does nothing to that call.

Instead, use objcopy to mark a weak and global so it can be overridden
by another implementation, but only for files originating in src/.

That way mocks - implemented in tests/ - become the source of truth.

TEST=Had such an issue with get_log_level() in a follow-up commit, and
the mock now takes over. Also, all existing unit tests still pass.

Change-Id: I99c6d6e44ecfc73366bf464d9c51c7da3f8db388
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2021-06-10 19:26:46 +00:00
Jakub Czapiga db4b21a1d0 tests: Add lib/cbmem_stage_cache-test test case
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Ie6851b9473b225beb5ba51e26f44e21ea5919a64
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54916
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-06-01 16:10:42 +00:00
Jakub Czapiga 5ab67f9ef8 tests/lib/memset-test: Add missing malloc check and free on error
Coverity found resource leak in test setup function in error block.
Add malloc result check and free in error handling to silence Coverity.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Found-by: Coverity CID 1446760
Change-Id: Icf746df27167047fa3cf8f5df09fced20863f76d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-05-26 12:33:25 +00:00
Jakub Czapiga d5433afb28 tests/lib/spd_cache-test: Initialize spd_block.addr_map
Coverity reported unitialized array spd_block.addr_map which values are
not used. Add initialization to silence Coverity and avoid errors in
the future.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Found-by: Coverity CID 1453145 1453146 1453147 1453148 1453149
Change-Id: If301f9e5d9e06ad26769bd0717f1f906e620d82d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-05-18 10:08:39 +00:00
Jakub Czapiga 2b8d7216ef tests: Add lib/spd_cache-test test case
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Ic9a1420e49e1e80d180117c931e630e54c90cd75
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-05-14 08:59:29 +00:00
Jakub Czapiga ce38084db6 tests/lib/crc_byte-test: Fix incorrect variable types
Some crc16_byte() and crc32_byte() tests had uint8_t instead of uint16_t
or uint32_t. That caused CRC values to be truncated and made tests
incorrect.
Also fix incorrect pre-calculated CRC values and change test buffer name
to more the accurate.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I61ee029a6950a8dfeb54520b634eaf4ed6bac576
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-05-05 11:45:45 +00:00
Jakub Czapiga a37c8021a6 tests: Add lib/rtc-test test case
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I2062e0d9dc2018bd6d8a210c8d26f2091e8c03fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-04-21 09:18:56 +00:00
Julius Werner c893197352 commonlib/region: Turn addrspace_32bit into a more official API
We had the addrspace_32bit rdev in prog_loaders.c for a while to help
represent memory ranges as an rdev, and we've found it useful for a
couple of things that have nothing to do with program loading. This
patch moves the concept straight into commonlib/region.c so it is no
longer anchored in such a weird place, and easier to use in unit tests.
Also expand the concept to the whole address space (there's no real need
to restrict it to 32 bits in 64-bit environments) and introduce an
rdev_chain_mem() helper function to make it a bit easier to use. Replace
some direct uses of struct mem_region_device with this new API where it
seems to make sense.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ie4c763b77f77d227768556a9528681d771a08dca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-04-21 02:06:26 +00:00
Jakub Czapiga 5d884837f4 tests: Add lib/coreboot_table-test test case
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I4d7d9ca43316bf514bb5ebd8909f441bcfa20eba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-04-18 20:43:05 +00:00
Jakub Czapiga dadcae63c6 tests: Add lib/dimm_info_util-test test case
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I536566ba883bbeb558587a8d71e3d86152fb5e14
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-04-15 07:38:05 +00:00
Jakub Czapiga ec8eef0a6b tests/lib/bootmem-test: Add initialization of lb_mem fields
Add missing initialization of tag and size fields. Include initial size
value in assertion in test_bootmem_write_mem_table().

Found-by: Coverity CID 1452250
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I27678a4eb01a0e6bedd0ba8c4b22a1b01afeaf12
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52263
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-04-13 16:03:27 +00:00
Jakub Czapiga 13145e5d18 tests/lib/malloc-test: Fix possible memory overrun
Coverity reported false-positive possible memory overrun
in setup_calloc_test(). Change memset address to use actual
buffer instead of pointer stored in symbol value in order
to silence Coverity.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I19f0718c657d565e515157e66367573e08f51254
Found-by: Coverity CID 1452005
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52136
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-11 21:05:25 +00:00