3 commits

Author	SHA1	Message	Date
Ronald G. Minnich	e8897c45a8	soc/riscv: Fix typo in src/soc/ucb/Makefile.inc. ... riscv builds again. Change-Id: I4caaee49c3eaa948540a916f684dd4e1ed9c9011 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/8026 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)	2015-01-01 18:07:14 +01:00
Kyösti Mälkki	aca2150a4f	UCB RISCV: Switch to DYNAMIC_CBMEM ... Change-Id: Iaaf68fd19f7b9a5b6849fffde3a9c68cb7862367 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7619 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>	2014-12-09 15:20:16 +01:00
Ronald G. Minnich	e0e784a456	Add UCB RISCV support for architecture, soc, and emulation mainboard.. ... Works in the RISCV version of QEMU. Note that the lzmadecode is so unclean that it needs a lot of work. A cleanup is in progress. We decided in Prague to do this as one thing, because it forms a nice case study of the bare minimum you need to add to get a new architecture going in qemu. Change-Id: If5af15c3a70733d219973e0d032746f8ab027e4d Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/7584 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)	2014-12-01 19:06:43 +01:00