This patch adds a check to determine if the CSE's current operation mode
is ME_HFS1_COM_SECOVER_MEI_MSG or not before sending HMRFPO_ENABLE
command to CSE. If CSE is already in the ME_HFS1_COM_SECOVER_MEI_MSG,
coreboot skips sending HMRFPO_ENABLE command to CSE to unlock the CSE RW
partition.
TEST=Verify sending HMRFPO_ENABLE command on Brya system.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I387ac7c7296ab06b9bb440d5d40c3286bf879d3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The patch renames the compare_cse_version() function to the
cse_compare_sub_part_version(). It makes the function generic so that
it can be used to compare version of any CSE sub-partition like IOM,
NPHY etc.
TEST=Verified build for Brya
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I88a44a3c0ba2ad8a589602a35ea644dab535b287
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59689
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce the `SOC_INTEL_ALDERLAKE_PCH_N` Kconfig option and use it to
specify the correct amount of PCIe I/O.
Document number 645550 indicates that Alder Lake-N has 12 PCH root ports
and no CPU root ports.
Document number 645548 indicates ADL-N has 5 clock sources and 5 clock
request signals.
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I7ebbcdcdb1ccc34b80ec71ac3e591fe4ad6b1904
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The VR configuration should be based on the different Soc SKU type. And
we also have different SKU in the same SA PCI ID.
Therefore, add TDP to recognize the correct SKU and give the correct
power setting.
BUG=b:202486131
TEST=Build and check fsp log to confirm the settings are set properly.
Signed-off-by: Curtis Chen <curtis.chen@intel.com>
Change-Id: I4d31e7afc76d9a8c772781671f92ec08f9d8713f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Guybrush uses secure counters to protect against High Definition (HD)
protected content rollback. These secure counters are hosted in TPM
NVRAM. Enable secure counters so that they are defined in PSP verstage.
BUG=b:205261728
TEST=Build and boot to OS in Guybrush. Ensure that the secure counters
are defined successfully in TPM NVRAM.
Change-Id: I6818c6f7905aa2eb815059e23c4f79437593f8ca
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The Alder Lake code currently supports the PCH-M and PCH-P types, which
have some differences (so far, only the amount of PCIe I/O). Mainboards
can use the `SOC_INTEL_ALDERLAKE_PCH_M` Kconfig option to specify which
PCH type they use: select the option to choose PCH-M, do not select the
option to choose PCH-P. While this works, it can be confusing once more
PCH types are added.
Introduce the `SOC_INTEL_ALDERLAKE_PCH_P` Kconfig option so that boards
have to explicitly choose a PCH type. Also, use this option to restrict
the PCH-P defaults for PCH-dependent settings to avoid unintended reuse
of the PCH-P defaults when adding a new PCH type. To make sure only one
PCH type is selected, add some preprocessor in `bootblock.h` to provoke
a build-time error if this requirement is not met. Kconfig doesn't seem
to have a mechanism to describe sets of mutually-exclusive bool options
that allows said options to be selected (a `choice` block doesn't allow
its elements to be selected). Finally, adapt the ADL boards accordingly.
Change-Id: I7deca820e08ce2b5a220f3c97a511a4f3464a976
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
This patch drops unnecessary `pmc_ipc.c` from Makefile as this
file is getting included upon CONFIG_PMC_IPC_ACPI_INTERFACE selection.
Change-Id: Ie66f0833daf033ec16210221610508f9fbb1e6c7
Signed-off-by: Subrata Banik <subi.banik@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59747
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Despite Stoneyridge being one only SoC in soc/amd that uses the first
generation of the PSP mailblox interface, this code is common for all
SoCs that use the first PSP mailbox interface generation, so move it to
the common PSP generation 1 code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I78126cb710a6ee674b58b35c8294685a5965ecd6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59701
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This part was copied from Picasso but Cezanne has some more bits used so
add the definitions now.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Icd128dca1ec30e7c70501c0e64482159be71cc7b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Both SPI_ROM_BIOS_SEMAPHORE and SPI_ROM_EC_SEMAPHORE bits in the
LPC_PCI_CONTROL are defined in the Stoneyridge BKDG #55072 Rev 3.04,
Raven1 and Picasso PPR #55570 Rev 3.18, Raven2 PPR #55772 Rev 3.08 and
Cezanne PPR #56569 Rev 3.03 which are all platforms that use this code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I855e640d020daf21c9f5b2f62a2ad0fd0274a575
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This patch replaces the use of the deprecated
cbfs_locate_file_in_region() API with the new
cbfs_unverified_area_map().
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: If4855280d6d06cf1aa646fded916fd830b287b30
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Adding USB addressmap for sc7280.
Use common USB driver for sc7280.
BUG=b:182963902
TEST=Validated USB enumeration on qcom sc7280 development board
Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
Change-Id: Ib92b74c8035a8c0148a9aa48e7870b261b832a33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Add common USB driver for qualcomm soc sc7180 and sc7280.
This includes dwc3 controller, qmp ss phy, qusb hs phy and snsp hs phy.
BUG=b:182963902
TEST=Validated USB enumeration on qcom sc7180 and
sc7280 development board
Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
Change-Id: I1013ded22855286220cfa747cb25418070fe85a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
When using 32 bit PCI accesses in lpc_enable_port80, we can use the
LPC_IO_OR_MEM_DECODE_ENABLE and DECODE_IO_PORT_ENABLE4 defines and don't
need to re-define bits with offsets from the beginning of the third byte
within this 32 bit register. This allows to drop the
LPC_IO_OR_MEM_DEC_EN_HIGH register definition which points to
LPC_IO_OR_MEM_DECODE_ENABLE + 2 and to drop the re-definitions of the
bit re-definitions with a different offset.
The code in lpc_enable_port80 was originally copied from sb/amd/agesa/
hudson/early_setup.c which might be sort-of a copy from what the AGESA
reference code does.
TEST=When commenting out SOC_AMD_COMMON_BLOCK_USE_ESPI in the Kconfig of
Mandolin and selecting AMD_LPC_DEBUG_CARD, all POST codes still get
shown on the POST code LED display when this patch is applied.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I001bb1c2ccf99e36d4fbd73d3bf96b78ddb87d67
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This function is unused and none of the SoCs using this code has a
physical PCI interface any more, so drop this function.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia5c5a8ec29264a075fefe75038ef2a84684d6427
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
PSP_MAILBOX_BAR is defined as PCI_BASE_ADDRESS_4, so use it instead of
PCI_BASE_ADDRESS_4 in the code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8658b674b9adea85dfc71d7036ccf3ae17464b58
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
PSPV2_STATUS_ERROR and PSPV2_STATUS_RECOVERY aren't used and the bit
definitions are also wrong, so drop those defines. For the PSP mailbox
interface version 2, struct pspv2_mbox is used to access the correct
status bits.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8e2aadfde00e2f7b0f99b462b8e3d6954959a584
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The checking register will be cleared after EC resets, so we move
bustracker dump from ramstage to bootblock, before triggering EC reset.
TEST=bustracker shows status before watchdog resets
BUG=b:207743045
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ic18dc9742cd9f657a035a374e28371dfc5f04ac3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
There will be no log in cbmem if we trigger ec reset on bootblock
stage. Therefore, call dcache_clean_all() before triggering ec
reset to flush cache to store logs on cbmem.
BUG=b:207743045
TEST=show logs on cbmem
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I1bd900beb4cc84f7121c5fb66907fa73b62517fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The patch enables cse_fw_sync() before DRAM initialization.
cse_fw_sync() sends HECI commands in order to set CSE's boot partition
and to trigger CSE firmware update.
As part of CSE firmware update, coreboot sends HMRPFO_ENABLE HECI
command. Since CSE supports the command after DRAM Initialization,
cse_fw_sync() is called after DRAM initialization.
Starting from CSE Litev16.0.15.1545, CSE support HMRFPO_ENABLE command
before DRAM initialization too. So, cse_fw_sync() is called before DRAM
initialization.
BUG=b:175516533
TEST=Dependency with CSE Litev16.0.15.1545 integration
Change-Id: Iad7403650df8bc4e40aa6e48ccfeba95a5789a2d
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55364
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch renames X86_AMD_INIT_SIPI Kconfig to leverage
the same logic (to skip 2nd SIPI and reduce delay between
INIT and SIPI while perform AP initialization) even on
newer Intel platform.
Change-Id: I7a4e6a8b1edc6e8ba43597259bd8b2de697e4e62
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56651
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Raise little CPU to 2GHz at romstage.
TEST=check little core cpu frequency is 2GHz
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: If4c983d15beb2b588230f3db7416cb767b29978d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The types of pwrap_read_field()'s return value and pwrap_write_field()'s
`val` argument are u16, so correct the usage in MT6366.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ie05ab65ecd9b8ea1379ef74393285c4f5d2db8a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
To raise little CPU frequency, add support for VPROC12 and VSRAM_PROC12 of MT6366.
TEST=build pass
BUG=b:202871018
Signed-off-by: James Lo <james.lo@mediatek.corp-partner.google.com>
Change-Id: I718fdf36d34969a6e21ddc8c1ec6f525e0e20904
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Map existing PCI_DEVICE_ID_INTEL_ADL_P_ID_1 to ADLP 4+4+2 45W SKU power
related settings.
Per doc#626774 ADL_MOW_WW46_2021, update PD optimization relaxation for
ADL-P 482(28W) and 442(45W).
BUG=b:193864533
TEST=Build and check fsp log to confirm the settings are set properly.
Signed-off-by: Curtis Chen <curtis.chen@intel.com>
Change-Id: Ieba738a8ad3da5ae0a115feaa275b997a219d731
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Adding the DP_ prefix to the defines for MMIO_NP, MMIO_WE and MMIO_RE
clarifies the scope of those definitions. For consistency also add this
prefix to MMIO_DST_FABRIC_ID_SHIFT.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3a509ccc071aa51a67552fb9e7195358a76fe4dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59627
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
On Picasso the MMIO_NP bit in the D18F0_MMIO_CTRL0 data fabric register
is bit 12, but that has changed to bit 16 in Cezanne.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I64c06b84e2c0737b259077e7932f418306638e19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The bit is called REF_CLK_OK_STATE and not RST_CLK_OK_STATE, so change
the name of the define to FCH_AOAC_REF_CLK_OK_STATE.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iae26db94d83ebb2cb799f6d3e0bec37c8e849219
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
There were only definitions for removing low, high or both glitches, but
not to not remove glitches, so add this too for completeness.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I650f7754546935539339c02bb6a94bb3f855d4ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
I found the name of the DEB_GLITCH_NONE definition a bit misleading, so
change it to DEB_GLITCH_REMOVE which should clarify what this will do.
The description for this value in the PPR/BKDG is "Remove glitch". This
also puts the define in line with GPIO_DEB_REMOVE_GLITCH which is the
only place where DEB_GLITCH_NONE/DEB_GLITCH_REMOVE is used.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I59648710e0ff28c2026e1b2cc7e433cafb2f2807
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Those methods were only in the non-common Stoneyridge GPIO ACPI code
that got dropped, so drop those unused methods too.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I519d88ffa1d5d4823cce4876ecf59b9019f676e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Stoneyridge uses the same GPIO bank peripheral as Picasso and Cezanne so
we can use the common AMD SoC GPIO ACPI code.
TEST=none
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifa1fc923cd5b779765917b171b5a7222f18a176a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
De-duplicate the definitions for the pin status bit and use this new
definition in both the C and the ACPI code.
TEST=Timeless build results in identical image for amd/mandolin.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8b0fe7dbec5dac176cdfa9690862433f202fb552
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The GPIO_WAKE_* definitions are the ones that are used in the code, so
drop the unused GPIO_*_WAKE_EN definitions for the same bits. Also move
the GPIO_WAKE_* definitions to the place the GPIO_*_WAKE_EN ones were
before this patch.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I622673cc72107908b525a65212061062f32e13dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
All bits covered by the bit masks GPIO_INT_ENABLE_MASK, GPIO_PULL_MASK,
GPIO_STATUS_MASK and GPIO_WAKE_MASK already have definitions in the code
so use those instead of magic numbers.
TEST=Timeless build results in identical image for amd/mandolin.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0bc9e1cecf2f063b42de3f8875fee421dd256648
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59593
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The definitions of GPIO_INT_ENABLE_STATUS_DELIVERY and
GPIO_TIMEBASE_62440uS fit into 96 characters, so remove the unneeded
line breaks.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4b9c3885259b9acf0539eed14e23fbbb0deccea7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The corresponding bit is marked as reserved in the following versions of
the documentation for all SoCs using this code:
Mullins: BKDG #52740 Rev 3.05
Stoneyridge: BKDG #55072 Rev 3.04
Raven1, Picasso: PPR #55570 Rev 3.16 & 3.18
Raven2: PPR #55772 Rev 3.08
Cezanne: PPR #56569 Rev 3.03
The old Rev 3.14 of the Picasso PPR #55570 had the bit 19 defined as
PullUpSel, but this is no longer the case in newer versions. It is
unclear if this got de-featured or if it was never present in the
silicon. To be consistent with the current documentation, drop this
define.
This patch also change the definition of GPIO_PULL_MASK to only cover
the bits used for the feature. The Cezanne PPR #56569 Rev 3.03 states a
default value of 0 for this bit after reset, so the resulting values in
the register aren't expected change. The other PPRs/BKDGs don't specify
a reset value for this bit, but it's likely safe to assume that all SoCs
that use the new GPIO interface use the same GPIO building block.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iaf2d4eec7a13e558c75d7edea343b876909a5b33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
On ADL, we actually use debug consent 2 for soc debug by DBC
Change-Id: Ie6fbf3cdcf5dcd1a11a895ea83f55157a2ac4eb9
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
