Commit Graph

25720 Commits

Author SHA1 Message Date
Elyes HAOUAS ddfccb4b9a nb/amd/agesa/family12: Get rid of device_t
Use of device_t has been abandoned in ramstage.

Change-Id: I265130532965c1655c34fd7dab6ca9ef0e27beca
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-05-20 09:15:47 +00:00
Elyes HAOUAS d9ef546269 sb/amd/pi/hudson: Get rid of device_t
Use of device_t has been abandoned in ramstage.

Change-Id: Iace820ad788fde7b230f63d95543470ce925b451
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26417
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-05-20 09:10:46 +00:00
Elyes HAOUAS 1a4abb73cd sb/amd/cimx/sb800: Get rid of device_t
Use of device_t has been abandoned in ramstage.

Change-Id: I2335b7e193663bb6c82bf267aaeb0b2367986f62
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-05-20 09:08:28 +00:00
Nico Huber 4a027e6e95 lib/gnat: Drop Restriction `No_Exception_Propagation`
It turns out that even with the `-gnatp` switch to suppress runtime
checks, the compiler is still allowed to generate them (it only doesn't
have to). If we can't control generation of checks, we also can't
make assumptions about propagation of their exceptions.

The compiler warning that led to this change seems spurious, though
(the check might be generated, but is dropped later). So we might
revert this decision if the compiler can be fixed.

Change-Id: I7470d74b1f96f90d0d15b24dfd636d5f1c778d46
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/26350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-19 20:39:09 +00:00
Jonathan Neuschäfer c4b614ca15 Documentation: Add mainboard section to index
Change-Id: Ib00bd6cdd13f164ca7eb07c9092e8d8fe17d23b1
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/26266
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-19 17:00:06 +00:00
Piotr Król 36c601b17b configs: add PC Engines apu2 sample configuration
Change-Id: Ia131c8aec1235443465bc017e11f59f38bef76db
Signed-off-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-on: https://review.coreboot.org/26118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-19 16:55:56 +00:00
Jagadish Krishnamoorthy 757a246ccd mb/google/octopus: enable xdci controller
BUG=b:79343083
BRANCH=NONE
TEST=On Yorp board, lspci should list xdci,
00:15.1 USB controller

Change-Id: I3a4878389a1b5b7abcaccf6ab16b67848aaaee83
Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Reviewed-on: https://review.coreboot.org/26358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-05-19 16:55:42 +00:00
ren kuo cbdbf01807 mb/google/reef/variants/: Add new memory ID
Add a new RAM ID of memrory PN:K4F6E3S4HM-MGCJ

BUG=b:78491470
TEST= emerge-coral coreboot chromeos-bootimage.

Change-Id: Ic40e36ab222572945f8588eb3df063e4fe0dbeb5
Signed-off-by: Ren Kuo <Ren.Kuo@quantatw.com>
Reviewed-on: https://review.coreboot.org/26365
Reviewed-by: Ren Kuo <ren.kuo@quantatw.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-19 16:55:22 +00:00
Kyösti Mälkki 967ed213dc via/vx900: Remove leftover code
Code is not used with EARLY_CBMEM_INIT and it
appears to have been invalid register anyways.

Change-Id: If0662937b38aec71292113ce8abd88da0b73feee
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-19 16:55:09 +00:00
Subrata Banik 8a25caee05 cpu/x86: Add support to run function on single AP
This patch ensures that user can select a specific AP to run
a function.

BUG=b:74436746
BRANCH=none
TEST=Able to run functions over APs with argument.

Change-Id: Iff2f34900ce2a96ef6ff0779b651f25ebfc739ad
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26034
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-19 01:16:06 +00:00
Subrata Banik e66600ee4f soc/intel/cannonlake: Add CONFIG_SMM_RESERVED_SIZE config
This patch ensures to make SMM_RESERVED_SIZE for cannonlake platform
else smm_subregion() returns 0 size.

Change-Id: I6a95a244bbcf40d672fd11d1c62e01224b2554f2
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2018-05-19 01:15:01 +00:00
Furquan Shaikh 8f567320ba util/cbmem: Fix compare function for qsort
compare_timestamp_entries will fail for entries that are different by
at least 2^32 since entry_stamp is 64-bit and the return for compare
is 32-bit. This change fixes compare_timestamps by actually comparing
the entries to return 1, -1 or 0 instead of doing math on them.

TEST=Verified that "cbmem -t" sorts entries correctly on previously
failing entries.

Change-Id: I67c3c4d1761715ecbf259935fabb22ce37c3966e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-18 20:13:47 +00:00
Furquan Shaikh 549080b8b3 arch/x86: Increase TIMESTAMP region size to 0x200
With the recent change 4c518e1 (timestamp: Add timestamps for TPM
communication) to add more timestamps for TPM communication, now we
are overflowing the TIMESTAMP region in verstage. This change
increases TIMESTAMP region size to 512 bytes to accomodate this.

BUG=b:79888151, b:79974682

Change-Id: I94c5403f256f0176d10ac61e9e1f60adf80db08b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-05-18 20:10:59 +00:00
Martin Roth 3abdeb0af0 Makefile.inc: Ignore IASL empty resource template warnings
As I mention in the comment, this is valid ASL, which was added as
a warning with the comment "This would appear to be worthless in
real-world ASL code."  While code using empty resource templates
could probably be rewritten, this seems like an arbitrary choice
to generate this as a warning, since it's valid.

This gets rid of warnings such as this one:
dsdt.aml   2975:    Return (ResourceTemplate() {})
Warning  3150 - Empty Resource Template (END_TAG only)

Which is generated by this code in google/rambi/acpi/mainboard.asl:
Method (_CRS)
{
  /* Only return interrupt if I2C1 is PCI mode */
  If (LEqual (\S1EN, 0)) {
    Return (^RBUF)
  }
  /* Return empty resource template otherwise */
  Return (ResourceTemplate() {})
}

Change-Id: I9cfe9069c738a284aa85feada9d58e1aee97e433
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26352
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-18 18:35:46 +00:00
Patrick Georgi e8604b8da6 libpayload: disable mouse on CHROMEOS
We already have that Kconfig flag, so I guess we should use it for
consistency.

Change-Id: I61ee6a97e369ccfe5c55d4414a5fa91c8d80ecf7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/26351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-05-18 16:00:18 +00:00
Duncan Laurie 283b01db40 mb/google/eve: Describe USB devices in devicetree
Describe the USB devices in the devicetree so they can get
generated into the SSDT and presented to the OS.

This was tested on an eve board and the resulting SSDT was
verified to show the expected values in _UPC and _PLD.

Change-Id: I292426f588ea74d61a5c4e4b01386bb18834c117
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/26176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-18 12:23:28 +00:00
Duncan Laurie 32bdffaf54 soc/amd/stoneyridge: Support ACPI USB code generation
To support generating USB devices in ACPI the platform needs to
know how to determine a device name for each USB port, and for any
root hubs that may be present.

The AMD Stoney Ridge platform has separate controllers for USB 2.0
and USB 3.0.  The USB 2.0 ports are connected through a hub to an
EHCI controller while the USB 3.0 ports are directly connected to
the xHCI controller.

This topology is described in ACPI and the port names are exposed
by the soc_acpi_name() function.

The USB controllers are configured to scan for static USB devices
in the devicetree and use the soc_acpi_name() function to identify
them.

Change-Id: I2bb677f84a49d2531929985dba319455b88e1686
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/26175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-18 12:23:17 +00:00
Duncan Laurie bf713b04b6 soc/intel: Add support for USB ACPI code generation
To support generating USB devices in ACPI the platform needs to
know how to determine a device name for each USB port, and for
any root hubs that may be present.

Recent Intel platforms route all ports to an XHCI controller
through a root hub.  This is supported by considering the root
hub to be USB port type 0, the USB 2.0 ports to be type 2, and
the USB 3.0 ports to be type 3.

This was tested with a Kaby Lake platform by adding entries to
the devicetree and checking the resulting SSDT.

Change-Id: I527a63bdc64f9243fe57487363ee6d5f60be84ca
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/26174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-18 12:23:04 +00:00
Duncan Laurie 4721f43390 drivers/usb/acpi: Add a driver for generating USB ACPI
Add a support for generating USB port descriptors for ACPI based
on their definition by the board in devicetree.cb.  This will
generate a _UPC and _PLD for each port, using a generic _PLD by
default.  The _PLD can also be customized for more accurate
descriptions if necessary.

This sample devictree.cb shows a USB 2.0 type-A port behind a root
hub connected to an xHCI controller:

device pci 14.0 on
  chip drivers/usb/acpi
    register "desc" = ""Root Hub""
    register "type" = "UPC_TYPE_HUB"
    device usb 0.0 on
      chip drivers/usb/acpi
        register "desc" = ""USB 2.0 Type-A""
        register "type" = "UPC_TYPE_A"
        device usb 2.0 on end
      end
    end
  end
end

It will generate the following ACPI code in the SSDT:

Scope (\_SB.PCI0.XHCI.RHUB.HS01)
{
  Name (_DDN, "USB 2.0 Type-A")
  Name (_UPC, Package (0x04)
  {
    0xFF,
    0x00,
    Zero,
    Zero
  })
  Name (_PLD, ToPLD (
    PLD_Revision           = 0x2,
    PLD_IgnoreColor        = 0x1,
    PLD_Red                = 0x0,
    PLD_Green              = 0x0,
    PLD_Blue               = 0x0,
    PLD_Width              = 0x0,
    PLD_Height             = 0x0,
    PLD_UserVisible        = 0x1,
    PLD_Dock               = 0x0,
    PLD_Lid                = 0x0,
    PLD_Panel              = "UNKNOWN",
    PLD_VerticalPosition   = "CENTER",
    PLD_HorizontalPosition = "CENTER",
    PLD_Shape              = "RECTANGLE",
    PLD_GroupOrientation   = 0x0,
    PLD_GroupToken         = 0x0,
    PLD_GroupPosition      = 0x0,
    PLD_Bay                = 0x0,
    PLD_Ejectable          = 0x0,
    PLD_EjectRequired      = 0x0,
    PLD_CabinetNumber      = 0x0,
    PLD_CardCageNumber     = 0x0,
    PLD_Reference          = 0x0,
    PLD_Rotation           = 0x0,
    PLD_Order              = 0x0,
    PLD_VerticalOffset     = 0x0,
    PLD_HorizontalOffset   = 0x0)
  )
}

Change-Id: I7024390e407fda4b195211bd4755bb5ca53b2b37
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/26173
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-18 12:22:50 +00:00
Duncan Laurie 8ccf59a947 acpi: device: Walk up the tree to find identifier
Instead of just checking the immediate parent for an device name,
walk up the tree to check if any parent can identify the device.

This allows devices to be nested more than one level deep and
still have them identified in one place by the SOC.

Change-Id: I9938fc20a839db91ff25e91bba08baa7421e3cd4
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/26172
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-18 12:22:40 +00:00
Arthur Heymans 4021a5acb3 nb/common/intel: Remove the mrc cache code
This is now unused, since all intel northbridges now use the
equivalent in drivers/mrc_cache.

Change-Id: I3e4b4afa53acc0a82b4ba961f13f816b04931fea
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23485
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-18 12:21:41 +00:00
Arthur Heymans dc71e25494 nb/intel/nehalem: Use the common mrc cache driver
The common mrc cache driver allows to save the raminit training
results to a separate fmap region which is more manageable than a
cbfsfile.

Change-Id: I25a6d3fe5466d142e3d10429a87b19047040c251
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-18 12:21:20 +00:00
Lijian Zhao 0e9bbcc905 intel/fsp: Update Cannonlake FSP header
Update Cannonlake FSP header to version 7.x.2E.50, the following changes
were made,
Memory Init UPD:
	1. Add GDXC configuration options.
	2. Remove some internal graphics memory selections.
	2. Remove Fixed mid option for SaGv.
	3. Add DualDimm per channel board type.
	4. Remove PEG IMR options.
Silicon Init UPD:
	1. Add CD clock selections of 675MHz.
	2. Remove Pcode PreWake/Rampup/RampDn time selections.
	3. Remove C3 state demotion/unDemotion selections.

BUG=None
TEST=Build and boot up on meowth platform.

Change-Id: I08ffb14df9f32089dbf44fa5bd3fc58a5bedb90d
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/26148
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-18 12:19:56 +00:00
Patrick Rudolph 65cbbe77ac arch/x86/acpigen: Fix corner case in _ROM generator
In case the Option ROM isn't a multiple of 4KiB the last buffer was
truncated to prevent a buffer overrun. But tests on nouveau showed
that nouveau expects a buffer that has the requested size and is zero
padded instead.

Always return a buffer with requested size and zero pad the remaining
bytes. Fixes nouveau on Lenovo W520 with Option ROM not being multiple
of 4 KiB.

Change-Id: I3f0ecc42a21945f66eb67f73e511bd516acf0fa9
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/25999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Rikken <nico@nicorikken.eu>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
2018-05-18 12:19:43 +00:00
Elyes HAOUAS 892e9f6030 sb/intel/i82801bx: Get rid of device_t
Use of device_t has been abandoned in ramstage.

Change-Id: I661b2435d9f0306b246a3e89aac24eb30c959085
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26253
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-18 12:18:07 +00:00
Elyes HAOUAS 152f1c918f sb/intel/i82801ax: Get rid of device_t
Use of device_t has been abandoned in ramstage.

Change-Id: I5c18fdc24bd0432f6b7a1131af68c792d377c3ac
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-18 12:18:03 +00:00
Elyes HAOUAS 97e8b754bf nb/intel/e7505: Get rid of device_t
Use of device_t has been abandoned in ramstage.

Change-Id: I2176ea83fac30052c02d9f6e98c89c40436a38e8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-18 12:17:54 +00:00
Elyes HAOUAS be841404cc sb/intel/ibexpeak: Get rid of device_t
Use of device_t has been abandoned in ramstage.

Change-Id: I7d9d0a205f9a650eb87bc8f90f2a28a5c4b2891c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-18 12:17:49 +00:00
Elyes HAOUAS 77f7a6e386 nb/intel/haswell: Get rid of device_t
Use of device_t has been abandoned in ramstage.

Change-Id: I10fb736a7406a6571dffce883fb82c2711526762
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-18 12:17:43 +00:00
Nico Huber 93323b303f cbfstool: Drop `-t` parsing for `add-payload` command
It seems this was never used and the usage doesn't mention it either.

Change-Id: I9240c0ed5453beff6ae46fae3748c68a0da30477
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26324
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-18 12:16:57 +00:00
Nico Huber ea83e3e9fe Makefile.inc: Drop spurious `-t` from `cbfstool add-payload`
The `-t` argument was never required for `add-payload` and results in
a warning now because the type was renamed.

TEST=Built with BUILD_TIMELESS=1 and compared binaries with and without
     this patch.

Change-Id: I6ccb70acc6e88a602b90c625040d4f05d8e3630a
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26323
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-18 12:16:53 +00:00
Chris Zhou 6e09b3bde9 mb/google/poppy/variants/nami: Fix SoC I2C CLK is abnormal
The I2C CLKs of SoC should be 400kHz, but waveform show 460kHz to
470kHz. Add I2C parameters to adjust I2C CLKs which 5% lower than
400kHz.

BUG=b:78819970
TEST=The I2C CLKs are 5% lower than 400kHz.

Change-Id: I2c3012b5b59c089801cda8fd7b0c433aad9df36d
Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/26282
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-18 12:16:20 +00:00
Nick Vaccaro a613ccd18b mb/google/poppy/variants/nocturne: enable pogo pin USB port
BUG=b:78122599
BRANCH=none
TEST="emerge-nocturne coreboot chromeos-bootimage" and verify pogo
pin port is working.

Change-Id: Ide7359366821f33c4746284e65cacdf4e240931d
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/26315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-18 12:15:12 +00:00
Hannah Williams 09b883f352 mb/google/octopus: Disable BT before S5 entry
The CNVi wifi/bt module prevents entry into S5 by keeping internal
SoC clocks running. Therefore it's necessary to disable BT prior to
S5 entry.

BUG=b:79606769
TEST= Test if BT device works under following cases:
1. Power-on
2. Press powerbtn before OS entry
3. Power-on from S5 again

Change-Id: Ibc14b4080a27de48d197e16d0eed162603482de2
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/26238
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-18 06:19:32 +00:00
Patrick Rudolph 5c3452b800 nb/intel/nehalem: Add ACPI path
Provide a valid ACPI path for coreboot's SSDT generators.

Fixes all ACPI errors found while booting GNU Linux 4.15 on
Lenovo T410.

Change-Id: Idd4986f39f21cb53cb019d0893d40fed94c6505b
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/26287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-05-17 14:26:53 +00:00
Martin Roth 735b9a0d1c util/abuild: Disable unspecified payload options
We have two payload options in abuild:
"None" or a pointer to an elf file.

This disables all other options in abuild, and makes disabling the other
options common to both valid options.

Change-Id: Icbd6fde4343ac1cff05778131f9e54370baf4224
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-05-17 12:06:33 +00:00
John Su b77cbbe1b0 mb/google/poppy/variants/nami: Update DPTF table
Update dptf.asl from tuning of the thermal team.

BUG=b:72974136
TEST=Match the result from DPTF UI.

Change-Id: I21ddc337359c3e11ad9756e61ba174b33dfc3c75
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/26209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-05-17 11:42:40 +00:00
Subrata Banik 1c9d8632fa soc/intel/skylake: Fix AP timeout issue while executing sgx_configure
Increase AP timeout limit for sgx_configure function. As per debug log
sgx_configure was not successful on all cores with given timeout value.

TEST=Ensures no timeout error in AP function execution.

Change-Id: Ia83f7a7eb6cd6c4808d55febfebe32724a633173
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@google.com>
2018-05-17 07:33:57 +00:00
Amanda Huang 13f8998026 mb/google/poppy: Disable one ALS node
Since there are two ALS device nodes on Nami, need to remove one.

BUG=b:79227879
BRANCH=master
TEST=Verify if only one ALS node is found in /sys/bus/iio/devices

Change-Id: I850af06bec833739afa0c8c516d351d81952ce2c
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/26271
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-17 07:01:14 +00:00
Patrick Rudolph eeb4e20b2f commonlib/cbfs: Make cbfsf_file_type public
Make cbfsf_file_type public to support detecting the payload type at
runtime. To be used by the following commits.

Possible payload types are:
* simple ELF
* FIT

Change-Id: I37e9fb06f926dc71b001722a6c3b6205a2f20462
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25859
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-16 21:29:56 +00:00
Patrick Rudolph 71327fbad8 lib/prog_loaders: Store CBFS type in struct prog
Store the type of the loaded program after locating the file and add a
method to retrieve the type.
Will be used to distinguish between SELF and FIT payloads.

Change-Id: Ic226e7e028d722ab9e3c6f7f1c22bde2a1cd8a85
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/26028
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-16 20:02:52 +00:00
Lubomir Rintel d8ec973fd2 vx900: Move to EARLY_CBMEM_INIT
To calculate the CBMEM address we need to determine the framebuffer
size early in the ROMSTAGE. We now do the calculation before
cbmem_recovery() and configure the memory controller right away.

If the calculation was done from cbmem_top() instead, we'd loose some
logging that seems useful, since printk() would recurse to cbmem_top() too
with CONSOLE_CBMEM enabled.

If we didn't configure the memory controller at this point, we'd
need to store the result somewhere else. However, CAR_GLOBAL is not
practical at this point, because calling car_get_var() from cbmem_top()
would recurse back to cbmem_top().

Change-Id: Ib9ae0f97f9f769a20a610f8d76f14165fb924042
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/25798
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-05-16 06:19:34 +00:00
Ivy Jian faafbfb81e mb/google/poppy/variants/nami: Load pantheon VBT binary
Load pantheon.bin by reading sku-id.

BUG=b:78663963
TEST=Boots to OS and display comes up.
     Check the board specific vbt binary loaded.

Change-Id: I66cb43d87363b3e8b1a1498cdae8eeeb8b75219d
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/26267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-16 05:13:09 +00:00
Ivy Jian aeb50d20c7 mb/google/poppy/variants/nami: Enable synaptics touchscreen support
BUG=b:74595040
BRANCH=master
TEST=
1. emerge-nami coreboot chromeos-bootimage
2. Booted on Pantheon with S7817 PCBa connected
3. Check touchscreen device is enabled by evtest
/dev/input/event4: SYTS7817:00 06CB:7817

Change-Id: Ic11684d5ed961af5eb704909f7d06eb0898068c2
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25915
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-16 05:13:05 +00:00
Ronald G. Minnich c6d134988c Revert "cbfs/payload type: Fix build warning and whitespace in name"
This reverts commit 717ba74836.

This breaks seabios and a few other payloads. This is not
ready for use.

Change-Id: I48ebe2e2628c11e935357b900d01953882cd20dd
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/26310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-16 04:50:55 +00:00
John Su 77a30af41c soc/intel/skylake: check DPTF_TSR1_ACTIVE_AC* in _ACx methods
Because thermal table is not included the values of DPTF_TSR1_ACTIVE_AC
from internal nami/vayne thermal team. Add conditional compilation
in _ACx methods if DPTF_ENABLE_FAN_CONTROL is defined in the dptf.asl.

BUG=b:72974136
TEST=Match the result.

Change-Id: I4b593118ca460a59aa49786cb99df417d135112a
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/26210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-15 15:50:20 +00:00
Naveen Manohar 532b8d5f25 soc/intel/apollolake: add rt5682 NHLT support
Add APIs and required parameters for creating Realtek 5682 SSP
endpoint in NHLT table.

BUG=b:79235534
TEST=check that NHLT table defined is created properly.
With the series merged & required driver support in kernel.
Verify Headset Audio playback.

Change-Id: Ic26a0b881f77af64ba00fd714b08c0f17c0acb3d
Signed-off-by: Naveen Manohar <naveen.m@intel.com>
Reviewed-on: https://review.coreboot.org/26057
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-15 15:49:29 +00:00
Patrick Rudolph ebdeb4d07d Documentation/Intel/NativeRaminit: Style fixes
Fix tables and minor markdown bugs.

Change-Id: I2ceb9614b516cbea19ab5e15ea7efabdfa3424bd
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/26276
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-15 15:48:18 +00:00
Martin Roth 5dbe8ee725 ACPI: Set the correct number of arguments in ACPI methods
These methods had unused arguments and could be corrected by
setting the correct number in the method initializer.

Change-Id: I86606cfa1c391e2221cee31994e83667fa9ead61
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-05-15 15:43:41 +00:00
Martin Roth 782c910e86 mainboard/amd/*: Remove unused arguments from SIOW ACPI method
Since the SIOW method doesn't use any arguments, don't pass it any,
and initialize it as not using any.

Change-Id: I3fa2ab8afb7d09c176a94bbd1db27587c36030cd
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26126
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-15 15:42:13 +00:00