Ronald G. Minnich
4bb8887ac4
change things that make no sense on ultra40. serial output now works!
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Signed-off-by: Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2453 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-13 19:58:52 +00:00
Yinghai Lu
7110f9261f
K8_4RANK to QRANK
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2445 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-05 06:59:56 +00:00
Yinghai Lu
d4b278c02c
AMD Rev F support
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2435 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-04 20:46:15 +00:00
Ronald G. Minnich
8a02b7d54e
add smsc part. Mod sun board to use smsc part for now
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2380 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-08-17 20:31:09 +00:00
Ronald G. Minnich
08af3f535d
mods for the ultra40 bringup. This now builds.
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amd gx2 north -- don't set anything in the north, it conflicts with vsa
settings. So we have our own pci_set_resources that is essentially a
no-op -- just calls the kids.
olpc rev_a config -- DISABLE the compressed rom stream. This SHOULD NOT
have been set -- it is untested and caused real trouble.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2369 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-08-09 02:21:49 +00:00
Ronald G. Minnich
e53d03c211
fix up the links for the ultra 40 -- i/o on ht 1 on each cpu
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2368 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-08-08 21:42:18 +00:00
Ronald G. Minnich
a758acab7f
fix up config space.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2367 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-08-08 18:02:12 +00:00
Ronald G. Minnich
90e68aef68
initial work on sunw ultra40. It's wrong :-)
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2366 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-08-07 20:02:02 +00:00
