GNUBoot/coreboot-kgpe-d16
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4 commits

Author SHA1 Message Date
Sven Schnelle
0860e723cb udelay: add missing bus frequency 
commit 5b6404e419 ("Fix timer frequency
detection on Sandybridge") reworked the udelay code, but didn't add
the 333MHz FSB entry used on Model 15 Xeons.

Change-Id: Ie34f9ae3703b64672625e7bf1b943654a7a5eaa6
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1099
Tested-by: build bot (Jenkins)
 2012-06-12 10:01:16 +02:00
Stefan Reinauer
5b6404e419 Fix timer frequency detection on Sandybridge 
Change-Id: Ide720bd91cde56a0afdd231d93500c371b1ffbe8
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/870
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
 2012-04-05 23:35:13 +02:00
Vikram Narayanan
6649d9740d This replaces the fixed shift values in the apic timer init with macros. 
Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6564 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-10 21:47:57 +00:00
Stefan Reinauer
4fbefdd1a9 * rework tsc based timer code to use inb instead of outb for calibration 
* Add generic Local APIC based timer code. This timer does not need expensive
  calibration and thus reduces the boot time by up to more than a second.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4446 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2009-07-21 21:19:06 +00:00