a long time ago. This will make it easier to port v2 boards forward to v3 at
some point (and other things)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3964 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
caused same filenames to still cause objects being dropped from the build list
- which was the whole purpose of the patch.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3962 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
similar to what v3 does. This is required to have two source files with
the same name but in different directories. (As in, two different SuperIOs on
board, with a superio.c each)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3961 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This patch converts mainboard_$VENDOR_$BOARD_ops to mainboard_ops and
mainboard_$VENDOR_$BOARD_config to mainboard_config.
Ron's part:
The config change that makes the naming change not break every build.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3954 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Elan SC520 requries us to deal with flash chip base addresses at locations
other than top of 4GB. The logic for that was incorrectly triggered also when
a board had more than one flash chip. This patch will honor flashbase only when
probing for the first flash chip on the board, and look at top of 4GB for later
chips.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3932 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
initialized same way as ICH7.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3926 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Thanks for the idea Mart!
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3921 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Thanks to Mart for spotting this!
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3920 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Test report from Julia. Thanks!
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Julia Longtin <juri@solarnetone.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3917 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
SST AAI is Auto Address Increment writing, a streamed write to the flash chip
where the first write command sets a starting address and following commands
simply append data. Unfortunately not supported by Winbond SPI masters.
From July 2008.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3913 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Developed and tested to work on Intel D201GLY in July 2008.
Tested by a helpful person on IRC whose name I've since forgotten. Sorry!
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Ward Vandewege <ward@gnu.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3910 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Through DirectIO from coresystems GmbH we now support Darwin/Mac OS X.
DirectIO is available at http://www.coresystems.de/en/directio
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3905 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3903 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The function exit()s on failure, and no callers check the return value.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3901 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
As reported by Jody McIntyre. Thanks!
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3894 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
parts.
This should help to reduce the code duplication for Rudolf's K8/VIA SMM
implementation...
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Joseph Smith <joe@settoplinux.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3870 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
board_pciid_enables more readable.
Signed-off-by: Stephan Guilloux <stephan.guilloux@free.fr>
> What real problem does this solve?
1. Next time someone adds a new struct member, we avoid mistakes of
ordering of initializers
2. we avoid mistakes in the first place.
The .x = y stuff was added for a (good) reason, I think this is an
improvement.
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3861 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This board has 2x MX25L8005 flash chips behind an IT8718F LPC->SPI bridge.
The board uses GIGABYTE's patented BIOS failover technology, and at this point
we do not know how to control which of the two chips flashrom actually hits.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Yul Rottmann <yulrottmann@bitel.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3859 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Stefan Reinauer