Now that chips and devices are treated differently and the device tree
actually contains only devices, next and nextdev are exactly the same
for all devices in the tree. This change gets rid of nextdev pointer
and updates all uses of nextdev to next.
BUG=b:80081934
TEST=Verified that static.c generated for all boards built by abuild
is same with and without this change.
Change-Id: Ie50b3d769a78fe0beddba2e5551441b43cb212a2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Now that chips and devices are treated differently in sconfig, this
change gets rid of struct header and add_header function which were
responsible for maintaining list of headers that need to be added to
static.c.
Instead, struct chip is re-factored into struct chip and
struct chip_instance, where chip is a list of unique chips required by
the mainboard whereas chip_instance is an instance of the chip. One
chip can have multiple instances dependending upon the devices in the
system. Also, struct device is updated to hold a pointer to chip
instance instead of the chip structure. This unique list of chips is
then used to add appropriate headers to static.c
BUG=b:80081934
TEST=Verified using abuild that all boards compile successfully.
Change-Id: I6fccdf7c361b4f55a831195adcda9b21932755aa
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26739
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a helper function s_alloc (sconfig alloc) that allocates memory
using calloc to get 0 initialized memory and checks to ensure it is
not NULL.
BUG=b:80081934
Change-Id: I56a70cf4865c50ed238226ace86e867bb1ec53db
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The only reason bus pointer existed in device structure in sconfig was
to allow a node to point to the parent which could be a chip and bus
which is the true parent in device tree hierarchy. Now that chip is no
longer a device, there is no need for separate bus and parent
pointers. This change gets rid of the redundant bus pointer in struct
device in sconfig.
BUG=b:80081934
TEST=Verified that static.c generated for all boards built by abuild
is same with and without this change.
Change-Id: I21f8fe1545a9ed53d66d6d4462df4a5d63023844
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change removes call to add_header from parsing functions and
moves it to a local function within main.c. It also adds a new
function emit_headers that is responsible for creating the linked list
for chip headers and emitting those to static.c
BUG=b:80081934
TEST=Verified that static.c for all files compiled using abuild is the
same with and without this change.
Change-Id: I24d526e81323115d3cc927242a4b9e49414afbe0
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26726
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change adds a new structure "struct chip" to identify elements of
type chip rather than re-using the structure for device. Until now
chip was treated as a device while generating the parse tree and then
device tree postprocessing skipped over all the chip entries in
children and sibling pointers of device nodes.
With this change, the device tree will only contain struct device in
the parsed tree. It helps by avoiding unnecessary pointers to chip
structure as children or next_sibling and then skipping those elements
in post processing. Every device can then hold a pointer to its chip.
When generating static.c, chip structure is emitted before device
structure to ensure that the device structure has chip within its
scope. Externally, the only visible change in static.c should be the
order in which chip/device elements are emitted i.e. previously all
chips under a particular device were emitted to static.c and then the
devices using those chips. Now, all chips are emitted before all the
devices in static.c
BUG=b:80081934
TEST=Verified that abuild is successful for all boards. Also, verified
that static.c generated for eve, kahlee, scarlet, asrock imb_a180 is
unchanged from before in node definitions.
Change-Id: I255092f527c8eecb144385eb681df20e54caf8f5
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The generated file .dependencies shall be removed on invocation of
'make clean' as the clean target aims to delete all generated files.
Change-Id: I4ec291fe84136bbdf1c2563cc10195846652a36d
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/26600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Run `git status` to let the user spot what is going on.
Change-Id: I154d964354872f922cd22b05a5d2231ca2504f25
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/22016
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
CPUID F6x will not support all MSRs on intel_pentium4_later.
Removed from pentium4_later and added as Pentium D.
Change-Id: Ic6ac0593607b6f87fe921ac52738dad5ee3457dc
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
- Add some directories and files to the ignore list
- Add the LGPL as a recognized header. It's used in some files that
were pulled into coreboot from other sources.
Change-Id: I53423205f1cbf142a294ee5d24e885741a44dfcd
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
It now looks like this:
Check that files have license headers (lint-stable-000-license-headers): success
Check for superfluous whitespace in the tree (lint-stable-003-whitespace): success
Check that C labels begin at start-of-line (lint-stable-004-style-labels): success
Change-Id: I9d1f6adebae5b68a51e89c2833f8713f0ffcb616
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/26703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
It's a white list (configured through $(top)/.clang-format-scope) with
the expectation that the list will grow over time.
Once everything is covered, we can turn off the white-listing and keep
everything enforced.
To not drive people crazy, only check the files their commit touched.
Change-Id: I52c7ea73fd36aaa46c0bfce928158e1cd6304540
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/26514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Instead of requiring the user to enter their root password to set the
created files to their user, create a new user inside the docker
container with the correct UID & GID and build with that.
Change-Id: Ibbeff00211e8cf653f48204d285e06bca39b5fd2
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
These files are supposed to contain trailing whitespace due to the patch
format. Also use the exclusion list in the pre-commit hook.
Change-Id: I8816c05ea703964a332915a0675096836957b242
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/26695
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Users can have non-default configurations as to how git diff et al are
presenting file names in diffs (default: a/ and b/ prefixes). checkpatch
expects that and trims the first element, so enforce that configuration
for the diff that's sent into it.
Change-Id: I099795119456a73c900b31ce191c2d9e898a5c7e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/26694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Martin Roth <martinroth@google.com>
We didn't bail out if configuring or building of GCC failed but run
`make install` and later steps instead. This resulted in very confusing
logs that concealed the actual error.
Change-Id: Ia064e0bfd96f0cbad391da3bb19e4dc304d988ff
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26496
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This allows one to compile intelmetool with support for older ME
versions by setting the OLDARC preprocessor definition.
For example, compiling with OLDARC enabled avoids the "ME: GET FW
VERSION message failed:" error on the Lenovo X201i (ME version 6.0).
Change-Id: I5eb0da7663e795f790e2723bb334447380724b56
Signed-off-by: Matthias Gazzari <mail@qtux.eu>
Reviewed-on: https://review.coreboot.org/26450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Because the tegra124 & tegra201 lp0 builds weren't junit tests, the
builds weren't actually picked up by jenkins, so any failures were
not previously reported.
Change-Id: Ie443ca713912d01ccf6921ce49f846d7297163ef
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/26422
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds a new "rawcompress" command to cbfs-compression-tool,
that works exactly the same as "compress" except that it doesn't add the
custom 8-byte header to the file. This can be useful if you need to
compress something into a format that coreboot's decompression routines
can work with, but it's not supposed to go into CBFS.
Change-Id: I18a97a35bb0b0f71f3226f97114936dc81d379eb
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/26337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch adds two minor improvements to the way cbfs-compression-tool
parses the compression algorithm type that is passed through the -t
option of the 'compress' subcommand. These improvements are intended
to prevent accidents and unexpected behavior when using the
cbfs-compression-tool, in particular in automated contexts such as a
Makefile rule.
In the first part of this patch, a return statement is inserted after
the 'if (algo->name == NULL)' check of the compress() function. This
causes the function to exit immediately and subsequently abort the
program when the algorithm type was not detected correctly. Previously,
execution would continue with the 'algo' pointer pointing to the zeroed
out stopper entry of the types_cbfs_compression[] array. The ultimate
effect of this would be to pass 0 as 'algo->type' to the
compression_function() function, which happens to be the same
enumeration value as is used for CBFS_COMPRESS_NONE, leading to a valid
compression function result that matches the behavior of no compression.
Thus, if a script calling cbfs-compression-tool compress contained a
typo in the -t parameter, it would continue running with an unintended
compression result rather than immediately exiting cleanly.
In the second part of this patch, the strcmp() function is replaced with
strcasecmp() when comparing 'algo->name' with the 'algoname' parameter
that was passed to the compress() function. strcasecmp() uses an
identical function signature as strcmp() and is thus suitable as a
drop-in replacement, but it differs in behavior: rather than only
returning a result of 0 when the two NULL-terminated input strings are
character by character identical, the strcasecmp() function applies a
weaker concept of identity where characters of the latin alphabet
(hexadecimal ranges 0x41 through 0x5a and 0x61 through 0x7a) are also
considered identical to other characters that differ from them only in
their case. This causes the -t parameter of cbfs-compression-tool
compress to also accept lowercase spellings of the available compression
algorithms, such as "lz4" instead of "LZ4" and "lzma" instead of "LZMA".
As an unintended but harmless side-effect, mixed-case spellings such as
"lZ4" or "LZmA" will also be recognized as valid compression algorithms.
(Note that since the character "4" (hexadecimal 0x34) of the "LZ4"
compression type name is not part of the above-mentioned ranges of latin
alphabet characters, no new substitutions become valid for that part of
the "LZ4" string with this patch.)
Change-Id: I375dbaeefaa0d4b0c5be81bf7668f8f330f1cf61
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/26389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Up to this point, junit.xml has only been used to build tools, as abuild
has handled the coreboot builds. To add additional tests not covered
by abuild, we need junit.xml to work with bare directories.
This also requires updating the build directory (BLD_DIR) for existing
builds using the junit.xml target.
Change-Id: If6e27e02e25e20f48e5a9372373de6058ca378dd
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/26421
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
compare_timestamp_entries will fail for entries that are different by
at least 2^32 since entry_stamp is 64-bit and the return for compare
is 32-bit. This change fixes compare_timestamps by actually comparing
the entries to return 1, -1 or 0 instead of doing math on them.
TEST=Verified that "cbmem -t" sorts entries correctly on previously
failing entries.
Change-Id: I67c3c4d1761715ecbf259935fabb22ce37c3966e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
It seems this was never used and the usage doesn't mention it either.
Change-Id: I9240c0ed5453beff6ae46fae3748c68a0da30477
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26324
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We have two payload options in abuild:
"None" or a pointer to an elf file.
This disables all other options in abuild, and makes disabling the other
options common to both valid options.
Change-Id: Icbd6fde4343ac1cff05778131f9e54370baf4224
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This reverts commit 717ba74836.
This breaks seabios and a few other payloads. This is not
ready for use.
Change-Id: I48ebe2e2628c11e935357b900d01953882cd20dd
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/26310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Currently, adding a payload to CBFS using the build system, the warning
below is shown.
W: Unknown type 'payload' ignored
Update payload type from "simple elf" to "simple_elf" and rename the
word "payload" to "simple_elf" in all Makefiles.
Fixes: 4f5bed52 (cbfs: Rename CBFS_TYPE_PAYLOAD to CBFS_TYPE_SELF)
Change-Id: Iccf6cc889b7ddd0c6ae04bda194fe5f9c00e495d
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/26240
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Registers IA32_MCi_xx are defined as architectural MSRs
since "P6 Family Processors" and should have model-agnostic
indexing.
Note that in IA32 architecture manual, names of these MSRs are
similarly swapped in the table of Intel Core Microarchitecture.
I take this is an error in the documentation only, and it got
copy-pasted across different CPU family files in the utility.
Change-Id: I227102875b5c3d6ac144ed23a3085f3c37dabd4a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26269
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If the timestamp entries are added out of order, the duration
calculation will be wrong.
AGESA collects timestamp data through all the stages. Then in AmdInitPost
it asks for a buffer to write TP_Perf_STRUCT into. agesawrapper will then
take the data and call timestamp_add on each entry. This results in
the entries being out of order.
TEST=Built firmware for grunt that manually added entries and then ran
cbmem -t/-T to verify the entries were in the correct order.
Change-Id: I6946a844b71d714141b3372e4c43807cfe3528ad
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/26168
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The VIA CPUs allow setting the CPUID vendor, which is best read as
a character string.
Change-Id: I67f77ca75f7d77e47b3ba09bad904df5805e373a
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/18257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
VIA c3 & C7 use the the family of 0x6 and model 10, but are not quite
Pentium III.
Change-Id: I85e9853b42cfd20db46db0bd244620d6813bc826
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/18256
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit adds support for describing USB ports in devicetree.cb.
It allows a USB port location to be described in the tree with
configuration information, and ACPI code to be generated that
provides this information to the OS.
A new scan_usb_bus() is added that will scan bridges for devices so
a tree of ports and hubs can be created.
The device address is computed with a 'port type' and a 'port id'
which is flexible for SOC to handle depending on their specific USB
setup and allows USB2 and USB3 ports to be described separately.
For example a board may have devices on two ports, one with a USB2
device and one with a USB3 device, both of which are connected to an
xHCI controller with a root hub:
xHCI
|
RootHub
| |
USB2[0] USB3[2]
device pci 14.0 on
chip drivers/usb/acpi
register "name" = ""Root Hub""
device usb 0.0 on
chip drivers/usb/acpi
register "name" = ""USB 2.0 Port 0""
device usb 2.0 on end
end
chip drivers/usb/acpi
register "name" = ""USB 3.0 Port 2""
device usb 3.2 on end
end
end
end
end
Change-Id: I64e6eba503cdab49be393465b535e139a8c90ef4
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/26169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Make sure that SiFive-related code is counted under RISC-V in the
release notes.
Change-Id: I3a74bb25ea66c98bc194adafd8267afeb42d7993
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25987
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In preparation of having FIT payloads, which aren't converted to simple ELF,
rename the CBFS type payload to actually show the format the payload is
encoded in.
Another type CBFS_TYPE_FIT will be added to have two different payload
formats. For now this is only a cosmetic change.
Change-Id: I39ee590d063b3e90f6153fe655aa50e58d45e8b0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
ifdtool has relied on one of the fields within FCBA(read_freq) to
determine whether a platform supports IFD_VERSION_1 or
IFD_VERSION_2. However, newer platforms like GLK and CNL do not have
read_freq field in FCBA and so the value of these bits cannot be used
as an indicator to distinguish IFD versions. In the long run, we need
to re-write ifdtool to have a better mapping of SoC to IFD fields. But
until that is done, this change adds a list of platforms that we know
do not support read_freq field but still use IFD_VERSION_2. This
change also updates GLK and CNL to pass in platform parameter to
ifdtool.
BUG=b:79109029, b:69270831
Change-Id: I36c49f4dcb480ad53b0538ad12292fb94b0e3934
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
I get the error below when using the following command in combination
with sudo:
sudo command -v $SOME_COMMAND
sudo: command: command not found
Detection of the cbmem path is working fine without sudo.
Change-Id: I8788c190ffebde117e2abd3df924c48d8f6fd05d
Signed-off-by: Matthias Gazzari <mail@qtux.eu>
Reviewed-on: https://review.coreboot.org/25989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The layout command prints all FMAP regions in the final image among with
the region size. Extend this command to show the offset of each region
in the image.
Change-Id: I5f945ba046bd2f1cb50a93e90eb887f60c6fde8a
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/25851
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Correct spelling mistakes and punctuation, and improve some wording.
Change-Id: I2c976bd62d8fa508373747b3fb3cf31490d5f631
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/25338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reduce the potential for confusion.
Change-Id: I1d5df9acb30948f786f4ced895bbaeed80153fdb
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
That caused the CFLAGS, CXXFLAGS, and '|| touch .failed' to not be taken
into account when building binutils.
Change-Id: I94521eb73cefdc5ed01fbf10122966a54cc28166
Signed-off-by: Vivia Nikolaidou <vivia.nikolaidou@puri.sm>
Reviewed-on: https://review.coreboot.org/25901
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It's what we use on coreboot.org to update
www.coreboot.org/Documentation
Change-Id: I6e5457d2e39a10f14fabd68bbb231a05e2f66f1d
Signed-off-by: Patrick Georgi <patrick@georgi.software>
Reviewed-on: https://review.coreboot.org/25869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
T32 scripts that allow debug of any coreboot stage on sdm845
Change-Id: Ia1bcbe687ca7bba10dc04cb6689640b13a8453f5
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/25542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
In order to help the reader understand where things are generated
from add a comment string that is composed of the command line
used to generate the files.
BUG=b:72728953
Change-Id: I1b93923f8b08192448ab19226fd27661cc09e853
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
We shouldn't have two of everything
Change-Id: I9879b40e26ba5a98626bc14c3d273fb525c070f7
Signed-off-by: Patrick Georgi <patrick@georgi.software>
Reviewed-on: https://review.coreboot.org/25870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
The FU540 is the first RISC-V SoC with the necessary resources to run
Linux (an external memory interface, MMU, etc).
More information is available on SiFive's website:
https://www.sifive.com/products/hifive-unleashed/
Change-Id: Ic2a3c7b1dfa56b67cc0571969cc9cf67a770ae43
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
There's no good reason to use the more complicated name.
Change-Id: I515e2df3b87580ddd31d18fe63451a98e92ead61
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25700
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If one wants to check in generated page tables in C then coreboot
complains about there not being a license. Therefore, add the BSD
license to the generated page tables.
BUG=b:72728953
Change-Id: I980d7a7c0c14c1ed5aa8ce37a1484943a6a100f2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
The linux kernel uses the following mapping for PAT entries:
PTE encoding:
PAT
|PCD
||PWT PAT
||| slot
000 0 WB : _PAGE_CACHE_MODE_WB
001 1 WC : _PAGE_CACHE_MODE_WC
010 2 UC-: _PAGE_CACHE_MODE_UC_MINUS
011 3 UC : _PAGE_CACHE_MODE_UC
100 4 WB : Reserved
101 5 WP : _PAGE_CACHE_MODE_WP
110 6 UC-: Reserved
111 7 WT : _PAGE_CACHE_MODE_WT
Update the page table generator to match what the linux kernel is
using. This just makes things consistent with linux.
BUG=b:72728953
Change-Id: Ie5ddab5c86d4e03688d7e808fcae34ce954b64f9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
There are boards that don't use ports 0x62 and 0x66 for EC, e.g. Dell
Latitude E6230 uses 0x930 and 0x934.
Change-Id: Ie3005f5cd6e37206ef187267b0542efdeb26b3af
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/23430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Add more verbose error message for common problems on modern
operating systems, like Secure Boot and CONFIG_STRICT_DEVMEM.
Change-Id: Ie3361910d48271bcc2cd3b4b74937fbc5df0a176
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Only try to unhide MEI if the PCI device wasn't found and
probe for RCBA before trying to use it.
Allows to run the utility on Skylake and newer hardware that
do not have RCBA any more.
TODO: Use sideband interface to unhide MEI.
Change-Id: I7926aa80b132d5be9fece0724516701d74dd4d3d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Don't crash if mapping MEI PCI memory fails.
This can happen if CONFIG_STRICT_DEVMEM is enabled.
Change-Id: I33c75a7cccb4cefaa26f70aed4bdc4bd620cdad0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Copy script from Linux added in commit 7683e9e5 (Properly alphabetize
MAINTAINERS file) by Linus Torvalds.
> This adds a perl script to actually parse the MAINTAINERS file, clean
> up some whitespace in it, warn about errors in it, and then properly
> sort the end result.
>
> My perl-fu is atrocious, so the script has basically been created by
> randomly putting various characters in a pile, mixing them around, and
> then looking it the end result does anything interesting when used as
> a perl script.
Change-Id: I2eb4e3f9863d0fe242fb690f1121842c80d72d6a
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/20742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
util/lint/lint creates a file using mktemp.
mktemp on OpenBSD requires at least 6 X's, while only 5 are in the template.
Change-Id: I0b80214dd83d21e12e16a5002c68127a7ca2e41b
Signed-off-by: Piotr Kubaj <pkubaj@anongoth.pl>
Reviewed-on: https://review.coreboot.org/19745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
OpenBSD needs the same includes as NetBSD. It also doesn't have x86_64_iopl
function, but amd64_iopl.
Change-Id: I28273d4d87a3a77cf35412a0695325c0535e42e5
Signed-off-by: Piotr Kubaj <pkubaj@anongoth.pl>
Reviewed-on: https://review.coreboot.org/19741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
As seen on ASUS P8Z77-V Pro
Change-Id: I9fce9a35174b5120f67c2345a0807db1b843eb48
Signed-off-by: Dan Elkouby <streetwalkermc@gmail.com>
Reviewed-on: https://review.coreboot.org/25661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The list of supported architectures in the usage output of cbfstool is
currently hardcoded and outdated.
Use the arch_names array in common.c to provide and up-to-date list.
Change-Id: I3e7ed67c3bfd928b304c314fcc8e1bea35561662
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25590
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Currently, "cbfstool -h | less" doesn't show any file types under
"TYPEs:". That's because the file types are printed with
print_supported_filetypes, which uses LOG, which prints to stderr. Use
printf print_supported_filetypes, and thus print to stdout, to make the
usage output more normal.
Change-Id: I800c9205c59383b63a640bc0798a1bd9117b0f99
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
coreboot doesn't support any Xivo boards, and their tree has been only
available as a tarball for a while. Let's remove this link from the
Supported Motherboards page's preamble.
It's still listed on https://www.coreboot.org/Supported_Motherboards/old.
Change-Id: I50e7bec02e803b62563f21384d857f1b37904dd1
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
corebootv4 vs. just coreboot has lost its significance. Version 4.0 has
been released in February 2010.
Change-Id: Ic2a35739e53fea411efc8691f1ba7db85ba0c764
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
checkpatch_json.py processes the output of checkpatch.pl &
generates json format output of comments.
This json format output can be used to post comment on particular
CL using gerrit.
BUG=None
BRANCH=None
TEST= Run following commands:
1. Capture output of checkpatch.pl to file say checkpatch.txt
nice -n 20 git diff HEAD~ | util/lint/checkpatch.pl --no-signoff -q - |
tee checkpatch.txt
2. Generate json format file for the output.
util/lint/checkpatch_json.py checkpatch.txt comment.json
3. Post the comment.json using gerrit
ssh coreboot.org gerrit review -j "<CL number>,<patchset number>" < comment.json
Change-Id: I2471792796ab8e7d9855a6559fc731345ebd1525
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/23429
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add dtc to Dockerimage for Jenkins.
Change-Id: Ifa3608f0a83431e75fbd402385863cce06e249fb
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25525
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Changelog:
* Add support for the HAP/AltMeDisable bit
* Add support for selective partition removal
* Fix the ME permission removal on gen. 3
* Add public key match
* Print the compressed size of the Huffman modules on gen. 2
* Wipe the ME6 Ignition firmware images
* Fix the removal of the last partition on ME6
* Various region size fixes
* Add manpage
* Add setup.py
* Print the value of the HAP/AltMeDisable bit
The output image should be identical, except for the platforms affected
by bugs (ME 6.x, but it's not supported by coreboot and ME 11.x with the
-d option, but it's not being used in our build process).
Overall, nothing should change when it's used with the
CONFIG_USE_ME_CLEANER option.
Tested on a Lenovo X220 and Sapphire Pure Platinum H61.
Change-Id: I3d5e0d9af0a36cc7476a964cf753914c2f3df9d2
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/25506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
This allows compiling the program using musl-libc, since otherwise
iopl(2) is undeclared.
Change-Id: Ia27203cf47b9be3f7bf1ad422c8f490caeae8f56
Signed-off-by: Ivan J. <parazyd@dyne.org>
Reviewed-on: https://review.coreboot.org/23834
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The default values used by ifdtool for setting region access control
do not match the expected values for SKL/KBL as per the SPI
programming guide. This change adds platform "sklkbl" that sets region
access control bits differently for SKL/KBL images.
BUG=b:76098647
BRANCH=poppy
TEST=Verified that the access control bits on KBL images is set
correctly.
Change-Id: I1328d8006c25be282b3223268d8f1fd0a64e2ed3
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Certain platforms need paging enabled during cache-as-ram because
dirty lines are being evicted by a heavy speculative frontend. Paging
needs to be enabled in order to utilize the NX (no execute) bit for
the regions that are strictly data (such as the stack). This utility
creates 32-bit PAE page tables using a static address space, and
the resulting tables have entries for all the PDPTEs such that it makes
it easy to enable 2MiB naturally aligned DRAM mappings once memory is
trained. Either binary files can be generated or C files. The pages that
are linked use a default base address of 0xaa000000 that can be changed at
runtime to reflect where the page tables are actually loaded. Or
specify a physical address on the command line that is known a priori.
iomap.txt:
0xd0000000, 0x100000000, UC, NX # All of MMIO
0xff000000, 0x100000000, WP, # memory-mapped SPI
0xffff8000, 0x100000000, WP, # XIP bootblock
0xfef00000, 0xfefc0000, WB, NX # CAR
0xfef40000, 0xfefc0000, WB, # verstage
0xfef20000, 0xfefc0000, WB, # romstage
0xfef40000, 0xfefc0000, WB, # fsp-m
$ go run util/x86/x86_page_tables.go --iomap_file=iomap.txt
Merged address space:
00000000d0000000 -- 00000000fef00000 UC NX : 375 big 256 small
00000000fef00000 -- 00000000fef20000 WB NX : 0 big 32 small
00000000fef20000 -- 00000000fefc0000 WB : 0 big 160 small
00000000fefc0000 -- 00000000ff000000 UC NX : 0 big 64 small
00000000ff000000 -- 0000000100000000 WP : 8 big 0 small
Total Pages of page tables: 5
Pages linked using base address of 0xaa000000.
BUG=b:72728953
Change-Id: I47625a24979b196011e2293712a8cdbdbb880d79
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/24919
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Funtion fstat will return -1 if there's any error, 0 if successful.
Check that fstat return is equal to 0, print error message and exit if
not 0.
This fixes CIDs 1353018 and 1353020
BUG=b:72062481
TEST=Build no errors
Change-Id: I83284d9125c75a29471f213f88b9181d5edba2e6
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23827
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Busybox mktemp does not support patterns with any characters after the XXXXXX
part. Drop the .o extension to make make-spike-elf.sh work on Alpine Linux.
Change-Id: I2e37ceef115c6d4d31eb617558481b2284dada83
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
In case of console dump for only the last boot, cbmem utility checks
for a list of regex in provided order. When pre-cbmem console
overflows, "Pre-CBMEM <stage> console overflowed.. " message is added
before "... <stage> starting" message. This change fixes the order of
regex in cbmem utility to match this.
Test=Verified on soraka that "cbmem -1" correctly dumps the data
starting from Pre-CBMEM romstage overflowed.
Change-Id: I9c5667bbd02ed3e93ac77a4f42e87d754a062919
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/23800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
board_status.sh was originally written for use cases where the DUT
is remote, i.e. accessed via serial port or SSH. This lead to some
issues when attempting to run the script on the DUT itself.
This patch attempts to handle the local use case more gracefully.
sudo is used when running the cbmem command, and the '-c' option
can be used to set cbmem path in case it's not in the default path
used by sudo.
Change-Id: I62957678ccae65fc46fd6ddf5ae92983d36cffad
Signed-off-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-on: https://review.coreboot.org/21566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
It doesn't make much sense to try and obtain dmesg via SSH if we're
using the serial port. Serial should only be used to obtain dmesg if
SSH is unavailable.
Change-Id: Iec70e64666f9446cf7e98a0fbcaa1cd5cefd8898
Signed-off-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-on: https://review.coreboot.org/21567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Martin Roth <martinroth@google.com>
When running 'make distclean' on coreboot, the build cleans the tools
as well. Since secimage didn't have a distclean target, it gave an error
that the distclean target didn't exist. This didn't actually affect
anything more than the secimage clean, but it was impossible to tell
that from the warning:
% make distclean
make[1]: *** No rule to make target 'distclean'. Stop.
Change-Id: I4b4bcc1ab48e767218d31e455d23527acedf4953
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
One of responsibilities of the `secimage` tool is signing the image
using the HMAC-SHA256 algorithm. The test being added verifies that
secimage's internal call yields same result as the according openssl
tool does.
Change-Id: I8de4328f435af56901a861e3d5e733657c3c7f78
Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
Reviewed-on: https://review.coreboot.org/23474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The registers were taken from the wrong addess since the spibar offset
was not added to it.
This also fixes the endianness.
Change-Id: I8bb91517770359599fe5f579c4686434da8d1c27
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23478
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
chromeec uses libftdi1-dev, so add it to the image.
Change-Id: I517e3f073062dcc6b0b8e3adaf7b0123290a1698
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
ff4025c5f "sb/intel/bd82x6x: Reduce function-disable mess"
Removed most of the writes to RCBA(FD) and renamed the function to
mainboard_rcba_config.
Writes to FD are properly handled in ramstage, so no need to do it in
romstage.
Change-Id: I4edb75569ceec2d2f1308755a66d286202ca0ae6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This fixes the warning that is seen on the jenkins server:
Insecure dependency in piped open while running setgid at
util/lint/checkpatch.pl line 958.
Change-Id: I476efa76ef6a275584a47ec0ecf2315948d53e9d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23473
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The `lint-extended-015-final-newlines` script skips over executable
files and thus leaves script files unchecked.
Use `file` to find scripts and include them in the `final newlines`
checks. Whitelisting is used including bash, perl, python and sh
scripts.
Change-Id: I8649b261b7e2cbbac7f9b90a9ace3f1c7b0eedeb
Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
Reviewed-on: https://review.coreboot.org/23325
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add support for a mmio resource in the devicetree to allow
memory-mapped IO addresses to be assigned to given values.
AMD platforms perform a significant amount of configuration through
these MMIO addresses, including I2C bus configuration.
BUG=b:72121803
Change-Id: I5608721c22c1b229f527815b5f17fff3a080c3c8
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Furquan Shaikh