This is the DRAM initialization code from the reference
implementation released by Mediatek for MT8192.
The DRAM calibration code can be taken as a standalone
library, used by different boot loaders for initializing
DRAM and following a different coding style (coreboot was
using Linux Kernel coding style), so we have to put it
in vendor code folder.
Signed-off-by: Xi Chen <xixi.chen@mediatek.com>
Change-Id: I3853204578069c6abf52689ea6f5d88841414bd4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
He practically is, so let's make it official.
Change-Id: I8adae5071f94ff309834fcab17b5a722e5c44b10
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Dabros <jsd@semihalf.com>
Add Nico Huber and Felix Singer as maintainers for the mainboards
siemens/chili and kontron/bsl6.
Change-Id: Ic70004d6f4c87b308246031429794312cc37107a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
The trailing slash is required to make gerrit add me on changes for the
whole tree, not just for the directory itself, which obviously would
only change if being deleted or renamed.
This also fixes the behaviour for Felix Singer.
Change-Id: I601aebd4335c7326deca0118725a6f25cec524a9
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
This patch adds a new CBFS implementation that is intended to replace
the existing commonlib/cbfs.c. The new implementation is designed to
meet a bunch of current and future goals that in aggregate make it
easier to start from scratch than to adapt the exisiting implementation:
1. Be BSD-licensed so it can evetually be shared with libpayload.
2. Allow generating/verifying a metadata hash for future CBFS per-file
verification (see [1][2]).
3. Be very careful about reading (not mmaping) all data only once, to be
suitable for eventual TOCTOU-safe verification.
4. Make it possible to efficiently implement all current and future
firmware use cases (both with and without verification).
The main primitive is the cbfs_walk() function which will traverse a
CBFS and call a callback for every file. cbfs_lookup() uses this to
implement the most common use case of finding a file so that it can be
read. A host application using this code (e.g. coreboot, libpayload,
cbfstool) will need to provide a <cbfs_glue.h> header to provide the
glue to access the respective CBFS storage backend implementation.
This patch merely adds the code, the next patch will integrate it into
coreboot.
[1]: https://www.youtube.com/watch?v=Hs_EhewBgtM
[2]: https://osfc.io/uploads/talk/paper/47/The_future_of_firmware_verification_in_coreboot.pdf
(Note: In early discussions the metadata hash was called "master hash".)
Change-Id: Ica64c1751fa37686814c0247460c399261d5814c
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38421
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add Michael Niewöhner as another maintainer for Clevo mainboards.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: Id3b35ddda13119149321e8c883e151176d8c520d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43655
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
MediaTek SoCs have been maintained by Hung-Te and team for a couple of
years now, let's update the documentation to reflect that.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I5adc9160409a98f90edcff6e7915ed3161d235c6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
The AM335X is a SoC, so should be in the soc tree.
This moves all the existing am335x code to soc/ and updates any
references. It also adds a soc.c file as required for the ramstage.
Change-Id: Ic1ccb0e9b9c24a8b211b723b5f4cc26cdd0eaaab
Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
I currently maintain System76 coreboot support.
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Change-Id: I4240618c9d9846c3b9e30db4d5ac725e1ca2a09c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43674
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Group entries by categories, and sort the groups alphabetically. Also,
separate different mainboard vendors with two extra spaces for clarity.
Change-Id: I43df8c24a40433357760827777497cbac4b6a919
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
I've got hardware to test things on these northbridges, and I am quite
familiar with their code.
Change-Id: Ied5adbb8bad94291a1843531be8a0923464d6212
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Ia48f20ca8c21d3c645c5566c189dddf2f8bc0308
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40966
Reviewed-by: Anjaneya "Reddy" Chagam <anjaneya.chagam@intel.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Bryant Ou <bryant.ou.q@gmail.com>
Reviewed-by: Johnny Lin
Reviewed-by: Morgan Jang
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit 991ee05 ("mb/gigabyte/ga-h61m-s2pv: rename to ga-h61m-series")
renamed the mainboard folder from `ga-h61m-s2pv` to `ga-h61m-series`,
but the MAINTAINERS file was not updated accordingly. Correct that.
Change-Id: I8119e29912e04ab57bebb96f37a4147afbb4d56e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
A space was missing before the asterisks.
Change-Id: I1cb62a9efc8e15c09cdebb49956f0edeb032beb3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40410
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
I will pass my responsibilities to Christian Walter.
I have hardly any time left for the coreboot project.
Change-Id: Ia60e71c5cbd361486dbc924ad954db203e285a5a
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This patch creates a new commonlib/bsd subdirectory with a similar
purpose to the existing commonlib, with the difference that all files
under this subdirectory shall be licensed under the BSD-3-Clause license
(or compatible permissive license). The goal is to allow more code to be
shared with libpayload in the future.
Initially, I'm going to move a few files there that have already been
BSD-licensed in the existing commonlib. I am also exracting most
contents of the often-needed <commonlib/helpers.h> as long as they have
either been written by me (and are hereby relicensed) or have an
existing equivalent in BSD-licensed libpayload code. I am also
relicensing <commonlib/compression.h> (written by me) and
<commonlib/compiler.h> (same stuff exists in libpayload).
Finally, I am extracting the cb_err error code definitions from
<types.h> into a new BSD-licensed header so that future commonlib/bsd
code can build upon a common set of error values. I am making the
assumption here that the enum constants and the half-sentence fragments
of documentation next to them by themselves do not meet the threshold of
copyrightability.
Change-Id: I316cea70930f131e8e93d4218542ddb5ae4b63a2
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
These are the boards I have and currently working on.
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I3f366105371c7d2568da6682b24cb52bce2d5467
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38026
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The MIPS architecture port has been added 5+ years ago in order to
support a Chrome OS project that ended up going nowhere. No other board
has used it since and nobody is still willing or has the expertise and
hardware to maintain it. We have decided that it has become too much of
a mainenance burden and the chance of anyone ever reviving it seems too
slim at this point. This patch eliminates all MIPS code and
MIPS-specific hacks.
Change-Id: I5e49451cd055bbab0a15dcae5f53e0172e6e2ebe
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34919
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add an entry for mb/supermicro/x11-lga1151-series and add myself to the
list of maintainers.
Change-Id: I634d251b4323c4f05edd553a9fa82e0f8c53773b
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
I haven't been active in coreboot, and coreboot-on-RISC-V in particular,
for quite a while, so let's update the MAINTAINERS file accordingly.
Change-Id: Ib65da0659ada94deed8756498a6948d1d1352ed0
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33619
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: ron minnich <rminnich@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since they're in charge of enforcing it, they should also get to see
when somebody attempts to change it.
Change-Id: I8c12dd0c27f7c3661e9755a5181db08563c8561f
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Add maintainers to the new vendorcode.
Change-Id: Ie3f99dd99c708f93bfcd19f52c57504e157e1eca
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Add maintainers to the new mainboard port.
Change-Id: I620ea424cc26fa0218a74052863ea30700789e1b
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Remove former Intel employee from maintainers of Braswell SoC.
Add 3mdeb and Eltan representatives as Braswell SoC maintainers.
Also mark Braswell SoC as maintained.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Id815db60e3718bf141abcc7923ea073bbab4a516
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Piotr Król <piotr.krol@3mdeb.com>
And remove some maintainers that aren't even registered to Gerrit.
Change-Id: I3a753b60eab6d7939c37181760bcfb4bc6e75f65
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/29472
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Guckian
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Xi Chen