Print an error message and return if an invalid QUP or BLSP is
encountered. This prevents a possible null pointer dereference
of spi_clk.
Change-Id: I374e15ce899c651df9c2d3e0f1ec646e33d4bdb2
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1401086
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34523
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Consider the following assignment:
u64 = s32
For positive values this is fine, but if the s32 is negative, it will be
sign-extended in the conversion to a very large unsigned integer. This
manifests itself in two ways in the following code:
First, gpu_pipe{a,b}_port_select are defined as int, and can have the
values 1 or 2. In the case when they have the value 2, the shift 2 << 30
will be a negative number, making it susceptible to the sign-extension
problem above. Change these variables to something more reasonable like
a uint8_t, which is unsigned.
Second, in any bit shift, any variable with width less than an int will
be implicitly promoted to an int before performing the bit shift.
For example, the variable gpu_pipea_power_on_delay is a uint16_t, and if its
highest bit is set, the shift gpu_pipea_power_on_delay << 16 will become
negative, again introducing the above problem. To prevent this, cast all
smaller variables to a u32 before the shift, which will prevent the
implicit promotions and sign extensions.
Change-Id: Ic5db6001504cefb501dee199590a0e961a15771b
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1229699, 1229700, 1229701, 1229702
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34487
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
BUG=b:112267918
TEST=Ran make help and verified build directory is no longer created
Change-Id: I4bb066b5c3b3d9a7bb19291ef928042b90f10440
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The build directory might not exist in the src dir.
BUG=b:112267918
TEST=make what-jenkins-does
Change-Id: I2d4fa6cc455592f92070796cd065cd66646d5ba9
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The logic for the calculation of plld.m is rather complicated, so do a
sanity check that it is non-zero before doing the division.
Change-Id: I60f49b8eed47a3de86713304bde7a4d3f3d935dd
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1260981
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
volt_str is used to print information about the RAM configuration
in report_common_dimm(), so let's print out "unknown voltage" if the
voltage isn't recognized rather than a garbage value.
Change-Id: I8e85917fd682e166172fbf10597bde4a8a11dfc7
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1393958, 1393982
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change the fletcher32 checksum calculation to match PSP and AGESA
implementations.
The symptom of the failure has only been noted in Picasso's BIOS
Directory Table, when a BIOS binary image of different sizes were
passed to amdfwtool. The PSP halts the boot process with the bad
BDT checksum, and if allowed to continue, AGESA asserts later due
to a failed BDT verification.
This version has been verified to produce the same result as found
at https://en.wikipedia.org/wiki/Fletcher%27s_checksum.
TEST=Build apu2, bettong, grunt and verify before/after amdfw.rom
is unchanged.
Change-Id: I2ba2c49a70aa81c15acaab0be6b4c95e7891234f
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
* Move armv7 RAM dection to a common place
* Enable it for all emulated platforms
* Use 32bit probe values and restore memory even on failure
* Use the new logic on the following boards:
** qemu-armv7
** qemu-riscv
Tested on qemu-system-riscv:
Fixes kernel panic due to wrong memory limits reported.
Change-Id: I37386c6a95bfc3b7b25aeae32c6e14cff9913513
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
We recently added the --asserts option to set asserts as fatal in abuild
but didn't add the flag to getopts, so it gets rejected as an invalid
argument.
Change-Id: Ic70e9a2bec039955cf62c175875598773ade2d3d
Signed-off-by: Martin Roth <martinr@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Add VBT 8.0.1038 binary.
Panel #10 is modified to support the 1200x1920 LCD panel.
This panel is configured as default.
LCD and HDMI are working fine.
BUG=N/A
TEST=booting Facebook FBG1701
Change-Id: If327e4e071df61b02fcec45213c2b700320ef269
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Use latest OpenSBI that include support for dynamic firmware loader.
That allows us to use OpenSBI similar to BL31 on aarch64:
* coreboot loads the payload
* coreboot loads OpenSBI ELF right before payload handoff
* OpenSBI does platform lockdown and provides runtime services
* OpenSBI hands control to already loaded payload
The uncompressed compiled OpenSBI code is about 41KiB.
Required to boot GNU/Linux on qemu-riscv as some instructions needs to be
emulated by SBI.
Change-Id: If7ed706bc54a75fb583a8aa46fdd61ae7d18c546
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Set FD bit if xHCI is disabled in devicetree.
Change-Id: I3d08ded10daea6d86857ebbbf3f8dcc85ebe9df4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add f81803A plus the capability to control the fan with any fintek SIO.
This will be done through a common API, though currently only F81803A will
have it implemented.
BUG=none.
TEST=Tested later with padmelon board.
Change-Id: I3d336e76bccc38452b1b1aefef5d4a4f7ee129a8
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Also don't define the default as this result in spurious lines in the
.config.
This also cleans up an unused Kconfig file.
In the generated config.h CPU_QEMU_POWER8 is gone as expected and
ARCH_RAMSTAGE_PPC64 moves a few lines, but the value stays the same.
Change-Id: I70b64e49e1ce07b8f30d9bbc493272bdfb3bb0bf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31314
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Load SSPM firmware and boot up SSPM.
BUG=b:80501386
BRANCH=none
Test=We can see "SSPM is alive" in ATF stage if SSPM enabled and ipi success
Change-Id: I9285034fc8ce38b40134f5eb7b986a663175e620
Signed-off-by: Erin Lo <erin.lo@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31835
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We are treating reg_val like a bit mask, so use bitwise or instead of
boolean or, and use |= to enable certain bits instead of overwriting the
whole variable.
Change-Id: Ia8c0ea5a58e25b3b58ed82caba20f8e49a30fb68
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1287070
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Based on updated schematics, change polarity of USI_INT, and add
the reset and enable GPIOs to the touchscreen ACPI node. The stop
GPIO can't be used with the current implementation of _ON, as the
way it's wired will cause power sequencing to fail.
BUG=b:137133194, b:138240502
BRANCH=none
TEST=Compiles, don't have next board rev to test with
Change-Id: I1dfb8e649418e4c5e9b897fb4bc11393adc21ea2
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Change-Id: I5aa3bb2c72dcf127d418c989f6b63c9b1f412f08
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
JENKINS_ABUILD_OPT is passed in abuild's command line
Change-Id: I5e7fbb77a3c6592a4414a6c1e3f7556c7e3a824c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
This enables fatal asserts, which can be useful to get better
diagnostics by the build tools (both compilers and static analysis.)
Change-Id: I1e1653f465fe1f545878d6eec83b8645dc17d9cb
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
The abuild command line can vary a lot depending on options and the line
became unwieldy (plus, it's on two lines because we run abuild twice),
so factor it out into a variable.
Change-Id: I102756fb95c93f542d534610bf9737a13ac1ad62
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
depthcharge prefers knowing where its input comes from
BUG=b:137378326
BRANCH=none
TEST=ctrl-d / enter to enter dev-mode works now.
Change-Id: I74b5be18c3583be17c73950ced93fad883690090
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
So far the bootsplash is only correctly rendered if the framebuffer is
set up as 1024x768@16.
Different resolutions did not show anything, differnent depth resulted
in the distorted images.
This commit removes this limit by using the actual framebuffer resolutions
and combines the code for x86 and yabel.
For the moment the bootsplash is still limited to VGA-OptionROM
framebuffer init.
It was tested in 1280x1024@32 on the wip razer blade stealth using the
intel vgabios.
Change-Id: I5ab7b8a0f28badaa16e25dbe807158870d06e26a
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34537
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Old comment did not match the pattern required
to not flag the fall-through as an error.
Change-Id: I2afaca969c295a5dc4389dad0ce898c87bb841a6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Pass `XGCCPATH` instead of individual programs as that is what the
Makefile expects.
Change-Id: I3267ec5259e9d37b2f3b0b8c126d173fc8b5a3ca
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
It can be useful to pass along to external projects, e.g. payloads.
Change-Id: I61c7bb162e2737a562cbef08b32ebbafd9cf1cb0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tianocore payload uses nasm. Supply it in the coreboot toolchain
instead of relying on system version.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I086cbe6c46f7c09b2a7a83e177b32fd1bdf99266
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33024
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Prevent implicit cast to pointers.
The compiler doesn't warn about the conversion from
integer to pointer without a cast, because SA_DEV_ROOT
is literally '0' and there seems to be an exception
for that conversion.
Change-Id: I64fc156e3b9f578414ad03a00edb7cf3e33205c1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Remove old hda_verb.c code copied from intel/kblrvp7, as it's
been superseded by the common block HDA implementation.
Fixes a null pointer error preventing the HDA codecs from being
initialized, as found in Coverity CID 1403651.
Test: build/boot Librem 13v2, verify functional audio
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Change-Id: I2fd5363aad027f215f93964bc6a85f00fea86c88
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34531
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Also including <types.h>, is supposed to provide stdint and stddef.
Change-Id: Iab605f6be4a48c10fa5aae7a1222520149ad1392
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33691
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Also including <types.h>, is supposed to provide stdint and stddef.
Change-Id: Id6d881055826044d04843ba165641131b9111342
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Also including <types.h>, is supposed to provide stdint and stddef.
Change-Id: I812d468c68b31917da5d406e2fb3b84bc6331b69
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The bus variable doesn't live outside the scope of this function, and is
only used as a convenient way for passing the pointers to all the
sub-functions, so it doesn't need to be allocated. Put it on the stack
instead.
Change-Id: I4370d77445952731d20f7d9a91803612f4d21aef
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1294801
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34499
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The "internal PME" wake-up source could be from integrated LAN,
HD audio/audio DSP, SATA, XHCI, CNVi, or an ME maskable host wake.
chromium:1680839 adds USB port details to the wake-up when the
XHCI causes the wake-up. Expand the logging for wake-up details to
identify and log the other wake-up sources with more details. Note that
wake on Integrated LAN (GbE), SATA, and ME Maskable Host Wake are not
in use on Hatch, so these will not be tested.
BUG=b:128936450
BRANCH=none
TEST=``FW_NAME=hatch emerge-hatch chromeos-ec depthcharge vboot_reference
libpayload coreboot-private-files intel-cmlfsp coreboot-private-files-hatch
coreboot chromeos-bootimage``
Ensure /build/hatch/firmware/image-hatch.serial.bin has been built.
Program image-hatch.serial.bin into the DUT using flashrom.
Switch the DUT to the console (Ctrl-Alt-F2, or use the AP console via
servo).
XHCI USB 2.0
* Plug a USB keyboard into a USB-A port
* ``powerd_dbus_suspend``
* Verify low power mode by issuing the ``powerinfo`` command on the EC
console (via servo). Expect to see ``power state 4 = S0ix``.
* Press a key on the USB keyboard
* ``mosys eventlog list`` shows:
12 | 2019-06-26 14:52:23 | S0ix Enter
13 | 2019-06-26 14:53:07 | S0ix Exit
14 | 2019-06-26 14:53:07 | Wake Source | PME - XHCI (USB 2.0 port) | 3
15 | 2019-06-26 14:53:07 | Wake Source | GPE # | 109
CNVi (connected to Wi-Fi):
* Enable wake on disconnect via ``iw phy0 wowlan enable disconnect``
* Set up a hotspot on an Android phone
* Connect the Chromebook to th hotspot
* ``powerd_dbus_suspend``
* Verify low power mode by issuing the ``powerinfo`` command on the EC
console (via servo). Expect to see ``power state 4 = S0ix``.
* Turn off the hotspot on the phone
* ``mosys eventlog list`` shows:
8 | 2019-07-11 10:58:17 | S0ix Enter
9 | 2019-07-11 10:59:17 | S0ix Exit
10 | 2019-07-11 10:59:17 | Wake Source | PME - WIFI | 0
11 | 2019-07-11 10:59:17 | Wake Source | GPE # | 109
XHCI USB 3.0
* TBD
HD Audio
* TBD
Change-Id: I2c71f6a56b4e1658a7427f67fa78af773b97ec7f
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34289
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Jacob Garber