When building a position independent executable (PIE) EBX is used
internally by the compiler to generate position independent address
references so it cannot be used in the clobber list. Use the already
existing code for the Darwin plattform for that case, too -- it'll
preserve the EBX value.
Change-Id: Ief6d4872b8cd990856a0e8227a88bb228782aced
Signed-off-by: Mathias Krause <mathias.krause@secunet.com>
Reviewed-on: http://review.coreboot.org/209
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Add support for dumping the MSRs on model_f2x and dumping GPIOs and PM
registers on ICH5. Add ICH5 and i865 to the supported chips list.
Enable the dumping of BAR6 on i865.
Sample output:
Disabling memory access:
$ sudo setpci -s 6.0 0x04.b=0x0
$ sudo ./inteltool -m | head -n 9
Intel CPU: Processor Type: 0, Family f, Model 2, Stepping 7
Intel Northbridge: 8086:2570 (i865)
Intel Southbridge: 8086:24d0 (ICH5)
============= MCHBAR ============
Access to BAR6 is currently disabled, attempting to enable.
Enabled successfully.
BAR6 = 0xfecf0000 (MEM)
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Acked-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6197 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- pmbase is on southbridge function 3 on I82371XX
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6128 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
while others dislike them being extra commits, let's clean them up once and
for all for the existing code. If it's ugly, let it only be ugly once :-)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
ICH6 Southbridge,
82915 Series Northbridge,
P4 6xx Series CPU
to inteltool
Tested on my Clevo D900T, based on ICH6 and i915P, with a p4 630
installed.
Signed-off-by: Pat Erley <pat-lkml@erley.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5469 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
Some minor modifications to allow 64bit/32bit compilation on Darwin
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4621 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* PMBASE dumping now knows the registers.
* Add support for i965, i975, ICH8M
* Add support for Darwin OS using DirectIO
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3794 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
immensly when they know more systems / cpus / chipsets
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3531 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Mathias Krause