The gnvs table only needs to be zeroized after init;
zeroizing an existing/populated table renders all I2C devices
completely non-functional.
TEST: boot Linux and observe all I2C devices functional
Change-Id: Id149ad645dfe5ed999a65d10e786e17585abc477
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17828
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
On this board i2c3 bus is connected to the display TCON, but it is
acting as the master when it has power so it can read from its own
EEPROM on the bus. In order to prevent any possible issues in S0
make these pins input on the SOC.
BUG=chrome-os-partner:58666
TEST=tested on eve board, but this bus was not used before so
there is no visible change in behavior.
Change-Id: Ide32f45ee33ca986fd3249a5161e01edf99d6e22
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17800
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Current ACPI code for UARTs uses the PNP_DEFAULT_PSC macro for _PSC
(current power state) methods. Override it to `Return (0)` (i.e. cur-
rent state is D0) as the IT8783E/F doesn't have power management.
Change-Id: I3c858dde287dbf7e5fc0c20abb1fd374887acdde
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/17791
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
On upcoming boards an optional pull up is applied on GPIO_10
to indicate if the board should have security features locked
down for a shipping system. Provide a weak pull down so that
all boards will indicate a logic 0 until the stronger pull up
resistor is stuffed.
BUG=chrome-os-partner:59951
BRANCH=reef
Change-Id: I6f514a69bccd05ca02480f3c30d0ad503a955b1e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17803
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
In the factory it's helpful for knowing when a system being
built is meant for release with all the security features
locked down. Provide support for exporting this type of pin
in the acpi tables.
BUG=chrome-os-partner:59951
BRANCH=reef
Change-Id: Iec70249f19fc36e5c9c3a05b1395f84a3bcda9d0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17802
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Set aclk_emmc and clk_emmc to 148.5MHz under hs400es mode, which could
improve stability like kernel.
CQ-DEPEND=CL:386527
BUG=chrome-os-partner:54377
BRANCH=none
TEST=build and boot on kevin
Change-Id: Iaa76d3ec1ab999eb317a9ab6c7e3525594b15b57
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e6eb1f56371aea51f2584a97bf817189d61090b2
Original-Change-Id: If4754d22e83a0f9a029fedca12f26ff5ae8d44e1
Original-Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/386865
Original-Commit-Ready: Julius Werner <jwerner@chromium.org>
Original-Tested-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/17790
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
BUG=chromium:595715
BRANCH=none
TEST=/build/$board/firmware/coreboot.rom has a zeroed out SHARED_DATA
region if it exists.
Change-Id: Ib1e6fd62bcf987872890c6d155287dcedb0b1f40
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e8a88bf744f44d034f8606a556014e2bee37eda1
Original-Change-Id: I0b59f1f0e2f8645000f83cb3ca7f49e4da726341
Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/417821
Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: https://review.coreboot.org/17789
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Chrome OS images have three firmware ID regions, to store version
information for the read-only and the two read-write areas. Fill them
with a suitable default and allow configuring a different scheme.
There's already an override in google/foster and google/rotor to match
the naming scheme used so far (in depthcharge).
BUG=chromium:595715
BRANCH=none
TEST=/build/$board/firmware/coreboot.rom has the expected values in the
regions.
Change-Id: I5fade5971135fa0347d6e13ec72909db83818959
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d2e3be81faa8d21f92325294530714a4b18a1b3e
Original-Change-Id: I2fa2d51eacd832db6864fb67b6481b4d27889f52
Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/417320
Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: https://review.coreboot.org/17788
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
So far, cbfstool write, when used with the -u/-d options (to "fill
upwards/downwards") left the parts of the region alone for which there
was no new data to write.
When adding -i [0..255], these parts are overwritten with the given
value.
BUG=chromium:595715
BRANCH=none
TEST=cbfstool write -u -i 0 ... does the right thing (fill the unused
space with zeroes)
Change-Id: I1b1c0eeed2862bc9fe5f66caae93b08fe21f465c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: baf378c5f2afdae9946600ef6ff07408a3668fe0
Original-Change-Id: I3752f731f8e6592b1a390ab565aa56e6b7de6765
Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/417319
Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: https://review.coreboot.org/17787
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
We never specified what value add-int should write by default.
Change-Id: I240be4842fc374690c4a718fc4d8f0a03d63003c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/17796
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
- Separate mma code for fsp1.1 and fsp2.0
and restructuring the code
- common code is placed in mma.c and mma.h
- mma_fsp<ver>.h and fsp<ver>/mma_core.c contains
fsp version specific code.
- whole MMA feature is guarded by CONFIG_MMA flag.
Change-Id: I12c9a1122ea7a52f050b852738fb95d03ce44800
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/17496
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This is a follow-on patch to commit 10141c30 -
(nb/intel/gm45: Use LAPIC udelay instead of custom version)
which removed the custom udelay from everywhere except SMM.
This patch removes it from SMM as well, and gets rid of the
gm45/delay.c file.
Change-Id: I7970bb5205f4aa10b38172ab5b9f8bcd6766c4e7
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17330
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Show an error if a symbol does not have a defined type.
This caused a problem of an undefined symbol in check_defaults, so
we just skip those symbols there as we can't verify the default pattern
without knowing the type.
Change-Id: I28711a77962e16f6fc89789400363edd0fdd0931
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17345
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Since we've removed them from the tree, add a check to keep them out.
Change-Id: I2995da765fee8796a297963d54a1c34f56376efe
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17658
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Overriding symbols within a .config is pretty common when doing
automated builds with various different options. The warning
text makes it sound like this is an issue, so change it to say
'notice' instead. We could get rid of it completely, but it's
not a bad thing to know that we have two copies of the same symbol
in the .config.
BUG=chrome-os-partner:54059
TEST=copy a disabled kconfig option to the end and set it to y.
See notice text instead of warning.
Change-Id: I9f575b2275233f638e42676263348c807e6515bd
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16691
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This patch sets PL2 override value to 15W in RAPL registers
and sets DPTF PL2 Max to 15W
BUG=none
BRANCH=reef
TEST=emerge-pyro coreboot
Change-Id: Ibadf0fa442f556d018c249b1cf88e29c4d57c97f
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/17779
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
- Update the junit.xml target to make it less util specific
- Add builds of coreboot internal payloads: nvramcui and coreinfo
Change-Id: I97fda909065659ab7fa4c8ee00d936d97b255bf7
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17014
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
- Show an error if a directory is added after the command line options
to catch scripts using the old parameters.
- If an invalid parameter is specified, show the parameter.
Change-Id: Ie8948361f1c51e89a99bdb13df8c554747cd521d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17741
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
cbroot was previously specified by just adding it to the end of the
command line with no explicit identifier. This change allows it to
go anywhere in the command line and adds the -R or --root identifier.
This makes the command line more consistent. Most of the time, this
argument isn't even needed, as the automatic detection finds cbroot.
Change-Id: I1d6fd8f51765d0d8b29be8af1e8105e06dd44cc8
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17740
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
- Indent with spaces for consistency
- Change lbroot to cbroot
- Remove incomplete list of options from usage line
- Capitalize first word of all option text
- Alphabetize options other than version and help
- Move version and help options to the end
Change-Id: Id5bd4db8d7e3705cbbb93895a46a3608cd1b09e2
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17724
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This cleans up the shellcheck warnings in abuild.
Warning count:
1 Unexpected ==.
1 Use "${var:?}" to ensure this never expands to / .
1 VARIABLE appears unused. Verify it or export it.
1 Use "$@" (with quotes) to prevent whitespace problems.
2 Consider using { cmd1; cmd2; } >> file instead of individual redirects.
2 Expressions don't expand in single quotes, use double quotes for that.
3 Prefer [ p ] || [ q ] as [ p -o q ] is not well defined.
4 $/${} is unnecessary on arithmetic variables.
5 Check exit code directly with 'if mycmd;', not indirectly with $?.
5 Use cd ... || exit in case cd fails.
11 Declare and assign separately to avoid masking return values.
13 Use $(..) instead of legacy `..`.
20 Don't use variables in the printf format string.
104 Double quote to prevent globbing.
Change-Id: I9c77e122435ba87ce3a4aee76b5022f7265f9ef2
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17722
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
soc_binding.h includes FSP headers which define NULL macro. Because of
this, including stddef.h after soc_binding.h results in NULL being
re-defined. Thus, include stddef.h in soc_binding.h to avoid having
users include stddef.h along with soc_binding.h.
Change-Id: I600083c5d8f672518beaa1119f14f67728a433aa
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17773
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Instead of hardcoding pci_mmio_size in the raminit code,
this makes it a parameter in the devicetree.
A safe minimum of 768M is also defined since using anything
less causes problems (if 4G of ram is used).
Change-Id: If004c861464162d5dbbc61836a3a205d1619dfd5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16856
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Don't use scratchpad registers when we have romstage_handoff
to pass S3 resume flag. Also fixes console log from reporting
early in ramstage "Normal boot" while on S3 resume path.
Change-Id: I2f1f05ef4fc640face3d9dc92d12cfe4ba852566
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17676
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Don't use scratchpad registers when we have romstage_handoff
to pass S3 resume flag. Scratchpad register was read too
late in ramstage so acpi_is_wakeup_s3() did not evaluate
correctly.
This fixes low memory corruption at 0x1000-0x102c and the lack
of coreboot tables (util/cbmem not working) after S3 resume.
This also fixes console log from reporting early in ramstage
"Normal boot" while on "S3 resume" path.
Change-Id: I2922a15a90d2f8272c3482579bdd96f8f33e9705
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17675
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Don't use scratchpad registers when we have romstage_handoff
to pass S3 resume flag. Also fixes console log from reporting
early in ramstage "Normal boot" while on S3 resume path.
Change-Id: I4e2eabc59ff87b7ed40cfc9885bbe0256fe4a695
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17674
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Adapt implementation from skylake to prepare for removal of
HIGH_MEMORY_SAVE and moving on to RELOCATABLE_RAMSTAGE.
With this change, CBMEM region is set early-on as WRBACK
with MTRRs and romstage ram stack is moved to CBMEM.
Change-Id: Idee5072fd499aa3815b0d78f54308c273e756fd1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15791
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The value for _size was not evaluated correctly if ramstage
is relocated, make the calculation runtime.
While touching it, move symbol declarations to header file.
Change-Id: I4402315945771acf1c86a81cac6d43f1fe99a2a2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17784
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Model 6ex are Core Solo and Core Duo CPUs (yonah) that never existed
with a LGA775 socket.
This reduces the size of the microcode from 180k to 168k.
Change-Id: Ic5b3d0e7c8009dab2dca477010c328274a818fed
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17120
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
This patch adds an API to find file by name from
any specific region of fmap.
Change-Id: Iabe785a6434937be6a57c7009882a0d68f6c8ad4
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/17664
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Make sure relocation code reaches DRAM before issuing any
SMIs. Snooping and cache coherency may have undefined
behaviour as CPUs do not have uniform MTRR layout yet.
Change-Id: I47a7d684e05ff8c1c2f1f6a5bf8c0bbc561d9eac
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17712
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Create postcar_frame object without placing stack in CBMEM.
This way same cache_as_ram.inc code can be used unmodified.
Change-Id: Ic5ed404ce268ee881e9893dd434534231aa2bc88
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17700
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fill in the NHLT ACPI OEM header fields to differentiate
different audio solutions on a per board basis. This handles
boards that share a firmware that are differentiated by
the SKU id and boards that have their own firmware. For the
latter, the Oem Table ID uses the VARIANT_DIR to differentiate.
"reef" is always used for Oem ID which is treated as more of
family in this case.
iasl -d shows the following on reef:
[00Ah 0010 6] Oem ID : "reef"
[010h 0016 8] Oem Table ID : "reef"
[018h 0024 4] Oem Revision : 00000008
BUG=chrome-os-partner:60494
BRANCH=reef
Change-Id: I5daa6f0306bc05e812a8737ce61ee37177a36b76
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17772
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
There are 2 gpios on reef-like boards that can be composed
into a SKU. Add support for identifying the SKU value using
the base 3 gpio logic. Also export the SKU information to the
SMBIOS type 1 table.
BUG=chrome-os-partner:59887,chrome-os-partner:60494
BRANCH=reef
Change-Id: I8bb94207b0b7833d758054a817b655e248f1b239
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17771
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Update abuild to allow for building saved miniconfig files.
If one or more config files exist for a platform under
coreboot/configs, they will be built instead of the automatically
generated default config.
The config filename needs to start with "config.$VENDOR_$BOARD" to be
picked up by the abuild script.
- Update to version 0.10.0
- Add -d parameter to specify the saved config file directory
- Break 2nd half of create_config function into update_config
to set the payload for saved config files.
- Unset new payload Kconfig options that could be set in a saved
config file.
- Update a bunch of MAINBOARD variable names to BUILD_NAME since
the build name isn't necessarily the same as the mainboard name.
- Split build_target into two functions - build_target and
build_config because one mainboard can now build multiple
configurations.
- Update remove target and call it directly from build_target()
instead of from build_targets()
Change-Id: I1a276d3e507b178f7dcd9dc125fa9c59f1ab47bd
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17590
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
For some reason the \n in the defconfig save error was not escaped.
Change-Id: I6a76b258f461a194fe17aae2b4fa04326b46d8d6
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17742
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
Test some config options that don't typically get tested.
Change-Id: Ie05c99411c8ce6462a6f5502b086ee2b72a4324b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17591
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
There is ongoing work to link SPI bus and devices in to the devicetree
so this can be generated, but for now put in the raw ASL code to
describe this controller so it can be used by the factory.
BUG=chrome-os-partner:55538
TEST=successfully load fpc1020 kernel module on eve board
Change-Id: I6641664e60fcf2c0bad4b3506c77513b26d7be2e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17776
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Previously privilege drop was happening "too early" and that caused some
PMC IPC programming (performed in FSP) to fail because sideband was
already locked out. This change set moves privilege drop to later stage,
after last FSP notify call.
BRANCH=reef
BUG=chrome-os-partner:60657
TEST=iotools rdmsr X 0x121, make sure they can't be read.
Also dmesg|grep -i IPC to make sure there are no errors related
Change-Id: Ia3a774aee5fbf92805a5c69093bfbd3d7682c3a7
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/17769
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Matt DeVillier