Commit Graph

30207 Commits

Author SHA1 Message Date
Kyösti Mälkki 2f944f4da4 mb/scaleway/tagada: Remove use of car_get_var()
Board has CAR_GLOBAL_MIGRATION=n and can use .bss for a
variable that was previously declared with CAR_GLOBAL.

Test for !defined(__PRE_RAM__) can be transformed into
ENV_RAMSTAGE here as the warnings about invalid bmcinfo
structure do not need to be repeated in SMM console, which
is generally disabled anyways due to DEBUG_SMI=n.

Change-Id: I6b63213484107fa0eeb0d952d8766916b44a3c4e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-26 20:54:39 +00:00
Jamie Chen ec88c5c688 soc/intel/common: Include cometlake EMMC controller ID
Add cometlake EMMC controller ID

BUG=none
BRANCH=none
TEST=none

Change-Id: I3943dad57918df3df7885c2e2d3a86ab0e1d6008
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-08-26 20:13:35 +00:00
Martin Roth 96c075a359 AUTHORS: Move src/arch/arm64 copyrights into AUTHORS file
As discussed on the mailing list and voted upon, the coreboot project
is going to move the majority of copyrights out of the headers and into
an AUTHORS file.  This will happen a bit at a time, as we'll be unifying
license headers at the same time.

Additional changes in this patch:
- Make sure files say that they're part of the coreboot project
- Move descriptions below the license header

Note that the file include/arch/acpi.h is a fantastic example of why
moving to the authors file is needed.  Excluding the guard statements,
it has 8 lines of copyrights for 3 function declarations.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I334baab2b4311eb1bd9ce3f67f49a68e8b73630c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34606
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-26 19:20:00 +00:00
Yu-Ping Wu 5bfb5cc485 google/kukui: Enable CHROMEOS_USE_EC_WATCHDOG_FLAG
Kukui AP doesn't remember if the last AP reset was due to AP watchdog.
We need to enable CHROMEOS_USE_EC_WATCHDOG_FLAG so that it will query
the reset reason from EC.

BUG=b:109900671,b:118654976
BRANCH=none
TEST=1. run 'mosys eventlog clear; stop daisydog; echo > /dev/watchdog'
     2. wait for watchdog reset
     3. check 'mosys eventlog list | grep watchdog'

Change-Id: I053cc7664bbaf0d3fcae26ba9481a0ad700dca90
Signed-off-by: You-Cheng Syu <youcheng@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-08-26 15:13:52 +00:00
Martin Roth 155c8023dd AUTHORS: Move src/arch/arm copyrights into AUTHORS file
As discussed on the mailing list and voted upon, the coreboot project
is going to move the majority of copyrights out of the headers and into
an AUTHORS file.  This will happen a bit at a time, as we'll be unifying
license headers at the same time.

Additional changes in this patch:
- Make sure files say that they're part of the coreboot project
- Move descriptions below the license header
- Fix some spacing

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Id5f26a73f0df366651c076a94975bce1fb321b70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34605
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-26 13:52:01 +00:00
Frans Hendriks 4a9cd2e237 mb/facebook/fbg1701/data.vbt: Correct EFP1 configuration
EFP1 is configured as 'DisplayPort with HDMI/DVI
compatibility'. Using this setting 4K monitor is configured
into lower resolution.

Change EFP1 setting to 'HDMI/DVI'
The next addtional small changes are made in VBT:
UEFI GOP Driver
    Child Device 2 = LFP
    Child Device 3 = EFP1/LFP
LFP Panel configuration Y-Res of Panel #10 = 1920

BUG=N/A
TEST=LCD and HDMI on Facebook FBG1701

Change-Id: Idc694b15ff94b83291a8c8252e269b7e6d96f87b
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35043
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-26 13:46:29 +00:00
Frans Hendriks 47cef8f95b vendorcode/eltan/security/lib: Always include cb_sha.c for bootblock
cb_sha.c depends on C_ENVIRONMENT_BOOTBLOCK.
Include cb_sha.c unconditional since C_ENVIRONMENT_BOOTBLOCK is default for
chipsets.

BUG=N/A
TEST=Boot Linux 4.20 and verify logging on Facebook FBG-1701

Change-Id: If93195596efe7d8f298430e67eb1cf79804b96fc
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
2019-08-26 13:46:13 +00:00
Matt DeVillier 4af1fe23f8 google/link: fix detection of dimm on channel 1
Changes to the sandybridge memory init code (both MRC
and native) now require SPD data on all populated channels
in order for dimms to be detected properly, so copy
spd_data[0] to spd_data[2], as LINK always has 2
channels of memory down.

Test: boot google/link, observe onboard RAM correctly
detected on both channels

Change-Id: Id01d57d5e5f928dfc1cd9063ab1625c440ef2bbe
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-08-26 13:45:32 +00:00
Asami Doi a5d9e7a628 mainboard/emulation/qemu-aarch64: Update DRAM_SIZE_MB
DRAM_SIZE_MB should be the maximum size (255GiB / -m 261120M)
that’s possible with QEMU on AArch64 virt because it tries to search
the DRAM_SIZE_MB range to find the true memory size.

Signed-off-by: Asami Doi <d0iasm.pub@gmail.com>
Change-Id: Id479c0b18d1e1adceecdcca13e36119b95617e6d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2019-08-26 07:15:06 +00:00
Asami Doi 06993ee729 lib: ramdetect: Register exception handlers for ARMv8
Register exception handlers to avoid a Synchronous External Abort
that is raised when you try to access a non-memory address on ARMv8.
An exception handler can jump over the faulting instruction.
This is the feature only for QEMU/AArch64.

Signed-off-by: Asami Doi <d0iasm.pub@gmail.com>
Change-Id: I09a306ca307ba4027d9758c3debc2e7c844c66b8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2019-08-26 07:14:03 +00:00
Aamir Bohra b0b99058cc soc/intel/cannonlake: Add config to disable display audio codec
FSP 1263 looks for UPD configuration of "AudioLinkHda"
if false it disables SDI# link for the codec.

Change-Id: I8330f47416e580bf6b9ca1faed1de5cd578d0e2e
Signed-off-by: Selma BENSAID <selma.bensaid@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35078
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-26 07:13:13 +00:00
Nico Huber 4a86b3b036 nb/intel/gm45: Call ddr3_calibrate_zq() only for DDR3 :)
Change-Id: I7d00ddf727e7250b767a1c4b58bf11b17e900fc1
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34828
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-26 07:12:13 +00:00
Kyösti Mälkki c99d3afe3e amdfam10: Remove use of __PRE_RAM__
Change-Id: I4215b27332034a3c07052db92e4abae55c3fe967
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-26 02:08:42 +00:00
Marty E. Plummer 1e02d73c73 3rdparty/ffs: add open-power ffs utils
These tools are used to manipulate open-power specific partitioning and
ecc algorithms.

Change-Id: I0657f76aab75190244d0e81c2b1a525e50af484d
Signed-off-by: Marty E. Plummer <hanetzer@startmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35007
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-25 07:37:11 +00:00
Wisley Chen 37ba3d1cf5 mb/google/octopus: Re-assign sku number for vortininja
Re-assign sku number for vortininja.

BuG=b:138177049
BRANCH=octopus
TEST=emerge-octopus coreboot

Change-Id: I3166a635151fcc7b2e3c0122fa05925cfa5df7d0
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-24 03:35:23 +00:00
You-Cheng Syu 85bb874c9c google/chromeos: Support AP watchdog flag from Chrome EC
After ChromiumOS CL:1293132 and CL:1295890, Chrome EC can store the flag
telling if the last reboot was triggered by AP watchdog for some boards
(e.g., Kukui).

This CL adds a new function google_chromeec_get_ap_watchdog_flag(),
which reads the AP watchdog flag from Chrome EC, and updates the tables
of reset causes and reset flags.

A new Kconfig option CHROMEOS_USE_EC_WATCHDOG_FLAG is added for
elog_handle_watchdog_tombstone() to determine if watchdog reset was
triggered by the AP watchdog flag from EC instead of the tombstone in
AP.

BUG=b:109900671,b:118654976
BRANCH=none
TEST=test with https://review.coreboot.org/c/coreboot/+/31843

Change-Id: I7a970666a8c6da32ac1c6af8280e808fe7fc106d
Signed-off-by: You-Cheng Syu <youcheng@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-08-23 20:23:19 +00:00
You-Cheng Syu 8d6ea6a491 ec/google/chromeec: Update ec_commands.h
Copy ec_commands.h directly from ChromiumOS EC repository (CL:1520574).

Since ec_commands.h already defines usb_charge_mode and only
USB_CHARGE_MODE_DISABLED is used in coreboot, enum usb_charge_mode is
removed from ec.h.

To avoid redefinition of the BIT macro, #ifndef check is added to
include/types.h.

BUG=b:109900671,b:118654976
BRANCH=none
TEST=emerge-kukui -j coreboot

Change-Id: I7ed5344fc8923e45e17c3e2a34371db6f80b079d
Signed-off-by: You-Cheng Syu <youcheng@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31885
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-23 20:22:04 +00:00
Philip Chen f6f4a8f8de mb/google/hatch/var/kindred:: Add enable signal for touch screen
In the next board version, we will use GPP_D9 as enable control for touch
screen.

BUG=b:137133946
TEST=build

Change-Id: I213d0878bfca1ce4059ec0393f59d8e79e1b274c
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35039
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-08-23 16:17:56 +00:00
Philip Chen 148ca3d030 mb/google/hatch/variants/kindred: Remove unused devices
sx9310 and FPMCU are not used in Kindred.

BUG=none
TEST=build

Change-Id: Ied09d4bdb899d991131a75d7c848ff8637022f53
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-08-23 16:17:43 +00:00
Matt DeVillier 52009a9d16 mb/google/rambi: update GPIO, RAM config for clapper
When upstreamed, GPIO and RAM config for clapper variant was taken
from an older branch, leading some boards to fail to boot.

Update based on chromium branch firmware-clapper-5216.199.B,
commit 362d845 [baytrail: implement baytrail technical advisory 556192]

Change-Id: I099ee2cd0833e4b9ab093663c4549c79ec044127
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34760
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-23 08:18:42 +00:00
Asami Doi 38a1286111 lib: hardwaremain: Call exception_init() as soon as possible
Call exception_init() before calling cbmem_initialize() because
ARMv8 on QEMU uses an exception handler to detect a ram size.

Signed-off-by: Asami Doi <d0iasm.pub@gmail.com>
Change-Id: If010234a6576414e7e174c075b599a4aa4c19eab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-23 08:17:43 +00:00
Patrick Rudolph eeb8e74944 arch/x86/acpi: Add acpi_device_hid
Allow a driver to return device specific _HID, which will be consumed by
acpigen in order to generate proper SSDTs.

Change-Id: Ibb79eb00c008a3c3cdc12ad2a48b88a055a9216f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35006
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-23 08:16:21 +00:00
Kane Chen 3d0df83133 Revert "mb/google/octopus: Disable WLAN prior the entry of S5"
This reverts commit 38dbd68920.

Reason for revert:
ODM helped to verify w/ BT runtime suspend disabled + revert this change
And issue is gone. so I revert this change

see the test result in
https://partnerissuetracker.corp.google.com/issues/136039607#comment32


Change-Id: I248e9613cc39247a2bb88270c234c7d36d0ff60f
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
2019-08-23 08:14:28 +00:00
Bernardo Perez Priego ab9a7c0c44 soc/intel/cometlake: Add ISH Device ID
This Device ID is specific to CML, since it is obtained by reading ISH
configuration RO register.
In order to export ISH to kernel PCI device tree, this number must be
included in list of devices supported.

Change-Id: I6d245f1b3f0d0cfec77c31033eb20f147fd3d870
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34687
Reviewed-by: Li1 Feng <li1.feng@intel.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-23 06:36:34 +00:00
Thejaswani Putta 51d9d6712e mb/google/drallion: Add two variants - arcada_cml & sarien_cml
These variants are to support the sarien and arcada boards
with CML SOC, the drallion variant will be used to support the
upcoming drallion board.

Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.com>
Change-Id: I766bdccb6f8b6924d6ae1abbe57035f4ff1f6f17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
2019-08-23 06:34:07 +00:00
Peichao Wang 652799b738 mb/google/kukui: Add panel for Kodama
Declare the following panel for Kodama:
- AUO B101UAN08.3

BUG=b:139699622
TEST=builds Kodama image and working properly

Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I3f688ffd0ece6afac08d353ab5a6cf1cf876b32f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35001
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-23 06:32:27 +00:00
Kyösti Mälkki a23a0388e6 AGESA: Restrict use of -fno-zero-initialized-in-bss
Only apply the flag for libagesa -class.

Change-Id: Ide46214d62b2b16e5e1deaa0796be784ed813095
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34885
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-22 17:21:19 +00:00
Julius Werner 277498c283 libpayload: usbmsc: Factor out usb_msc_force_init() function
We're planning to have a use case with a custom USB device that
implements the USB mass storage protocol on its bulk endpoints, but does
not have the normal MSC class/protocol interface descriptors and does
not support class-specific control requests (Get Max LUN and Bulk-Only
Reset). We'd like to identify/enumerate the device via
usb_generic_create() in our payload but then reuse all the normal MSC
driver code. In order to make that possible, this patch factors a new
usb_msc_force_init() function out of usb_msc_init() which will
initialize an MSC device without checking its descriptors. It also adds
some "quirks" flags that allow devices registered this way to customize
behavior of the MSC stack.

Change-Id: I50392128409cb2a879954f234149a5e3b060a229
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-08-22 10:37:26 +00:00
Julius Werner 182fea717e libpayload: usbmsc: Skip zero-length packets at end of data
Some broken USB mass storage devices send another zero-length packet at
the end of the data part of a transfer if the amount of data was evenly
divisible by the packet size (which is pretty much always the case for
block reads). This packet will get interpreted as the CSW and screw up
the MSC state machine.

This patch works around this issue by retrying the CSW transfer when it
was received as exactly 0 bytes. This is the same mitigation the Linux
kernel uses and harmless for correctly behaving devices. Also tighten
validation of the CSW a little, making sure we verify the length before
we read any fields and checking the signature in addition to the tag.

Change-Id: I24f183f27b2c4f0142ba6c4b35b490c5798d0d21
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34485
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-22 10:36:48 +00:00
Julius Werner c788ae328e rockchip: Use new buffer_to/from_fifo32(_prefix) helpers
This patch changes the Rockchip SPI and I2C drivers to use the new
buffer_from_fifo32()/buffer_to_fifo32_prefix() helpers when accessing
their FIFOs (mostly just to demonstrate that/how the helpers work).

Change-Id: Ifcf37c6d56f949f620c347df05439b05c3b8d77d
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-08-22 10:36:31 +00:00
Julius Werner db7f6fb752 Add buffer_to/from_fifo32(_prefix) helpers
Many peripheral drivers across different SoCs regularly face the same
task of piping a transfer buffer into (or reading it out of) a 32-bit
FIFO register. Sometimes it's just one register, sometimes a whole array
of registers. Sometimes you actually transfer 4 bytes per register
read/write, sometimes only 2 (or even 1). Sometimes writes need to be
prefixed with one or two command bytes which makes the actual payload
buffer "misaligned" in relation to the FIFO and requires a bunch of
tricky bit packing logic to get right. Most of the times transfer
lengths are not guaranteed to be divisible by 4, which also requires a
bunch of logic to treat the potential unaligned end of the transfer
correctly.

We have a dozen different implementations of this same pattern across
coreboot. This patch introduces a new family of helper functions that
aims to solve all these use cases once and for all (*fingers crossed*).

Change-Id: Ia71f66c1cee530afa4c77c46a838b4de646ffcfb
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-08-22 10:36:22 +00:00
Hung-Te Lin 54ff1a0ad3 mb/google/kukui: Add flapjack panels
Add panels supported by flapjack.

Change-Id: I547bf6f26bdbfed52a00c8cfb268d4e7c17ed889
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-22 10:35:56 +00:00
Kyösti Mälkki 7cd2c07317 ACPI S3: Depend on RELOCATABLE_RAMSTAGE
With RELOCATABLE_RAMSTAGE, S3 resume path only uses
memory that is reserved from OS. So there is no need
for low memory backup and recovery.

Change-Id: If7f83711685ac445abf4cd1aa6b66c3391e0e554
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/26834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-22 06:38:13 +00:00
Kyösti Mälkki 546a2e8468 ACPI S3: Drop ACPI_HUGE_LOWMEM_BACKUP
ACPI S3 resume path can only modify low memory where
the non-relocatable ramstage resides, there is no need
to maintain a bigger backup copy.

Change-Id: Ifae41b51b359010ec02269c674936a87bd15623b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/15476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-22 06:34:02 +00:00
Kyösti Mälkki a963acdcc7 arch/x86: Add <arch/romstage.h>
Start with moving all postcar_frame related function
declarations here from <arch/cpu.h>.

Change-Id: I9aeef07f9009e44cc08927c85fe1862edf5c70dc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34911
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-22 02:50:35 +00:00
Hung-Te Lin 9ede2ffee8 mb/google/kukui: Move panel description to CBFS files
The panel description may be pretty large (for example, 1.3k for BOE
TV101) due to init commands and we should only load the right config
when display is needed.

BUG=None
TEST=make -j; boots and see display on Krane.

Change-Id: I2560a11ecf7badfd0605ab189d57ec9456850f75
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-21 22:58:45 +00:00
Hsin-Hsiung Wang e804695c6a mediatek/mt8183: add scp voltage initialization
Add scp voltage initialization.

BUG=b:135985700
BRANCH=none
Test=Boots correctly on Kukui and scp can boot up normally

Change-Id: I5afb60af3c14490e20f28f1c089cfca42ddf7fcf
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-08-21 18:12:15 +00:00
Arthur Heymans 4c095fc9e9 cpu/intel/car: Make stack guards more useful on C_ENV_BOOTBLOCK
With C_ENVIRONMENT_BOOTBLOCK, CONFIG_DCACHE_BSP_STACK_SIZE needs to be
set to define a stack region that can be shared over all stages using
CAR. It makes sense to use that Kconfig option's value instead of a
hardcoded value. This will result in less false positives when the
stack size is big, for instance with FSP using the coreboot stack.

In many configurations with C_ENVIRONMENT_BOOTBLOCK the stack_base is
at the base of CAR. If the stack grows too large it operates out of
CAR, typically resulting in a hang. Therefore the stack guards are
extended to cover 256 bytes at the base to at least provide a warning
when the romstage is dangerously close of running out of stack.

Change-Id: I2ce1dda4d1f254e6c36de4d3fea26e12c34195ff
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-08-21 16:38:17 +00:00
Kyösti Mälkki c2741855af arch/x86: Rename some mainboard_romstage_entry()
These platforms use different signature for this function, so
declare them with different name to make room in global namespace.

Change-Id: I77be9099bf20e00ae6770e9ffe12301eda028819
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34909
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-21 16:37:33 +00:00
Lijian Zhao 16562cb859 payloads/tianocore: Enable UEFIPayload
corebootpayload package in upstream TianoCore was replaced with
UEFIPayload, add external payload build option for UEFIPayload.

BUG=N/A
TEST=Select TianoCore payload as UEFIPayload, build and able to boot up on
QEMU q35 after PCIE_BASE set.

Change-Id: I0b7785fde9f4113b2cd91323ac0358b229c5a6e6
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34459
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-21 09:34:27 +00:00
Tim Wawrzynczak 44348185d9 soc/intel/common/smm: Add missing printk statement
SMI trap handler was missing a printk statement, which caused
Coverity to flag "data &= mask;" as a redundant operation.

Change-Id: I71da74e5e08e7d7e6d61c1925db19324efd73f0a
Found-by: Coverity CID 1381621
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-08-21 09:34:17 +00:00
Joel Kitching 220ac049ba vboot: update vboot2 functions to use new vb2_error_t
To make explicit when vboot2 error codes should be returned,
use the new vb2_error_t type on all functions which return
VB2_ERROR_* constants.

Additionally, add required vboot submodule commit id e6700f4c:
    2019-07-31 14:12:30 +0800 - (vboot: update vboot2 functions to use new vb2_error_t)

NOTE: This patch was merged separately on the Chromium tree:
https://chromium-review.googlesource.com/c/1728499

BUG=b:124141368, chromium:988410
TEST=make clean && make test-abuild
BRANCH=none

Change-Id: I804c2b407e496d0c8eb9833be629b7c40118415c
Signed-off-by: Joel Kitching <kitching@google.com>
Cq-Depend: chromium:1728292
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-21 09:32:45 +00:00
Joel Kitching 057d1b9d7e Update vboot submodule to upstream master
Updating from commit id 9c906110:
2019-08-06 06:07:01 +0000 - (vboot/tpm: fix return type inconsistencies)

to commit id a5afd01f:
2019-08-08 11:02:44 -0700 - (Minor fixes for clang)

This brings in 6 new commits.

Change-Id: Ic334ce8a5f24a0119fa2aaf000ce76c4c9e4932a
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-21 09:32:14 +00:00
Maxim Polyakov 0ebf32e207 soc/intel/common: use PAD_BUF() inside PAD_CFG_* macros
Use PAD_BUF() to disable the input/output buffer inside PAD_CFG_* macros
instead PAD_CFG0_RX_DISABLE/PAD_CFG0_TX_DISABLE

[1] https://review.coreboot.org/c/coreboot/+/34337

Change-Id: I19fd993e1f60d80eab0ce51eaed5e74ce1c6a34d
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-21 09:31:59 +00:00
Maxim Polyakov 8981c809e8 soc/intel/common: gpio_defs: set trig to disable in PAD_NC
There is no need to change the default value for the RX Level/Edge
Configuration parameter if the pad is not used/connected (PAD_NC)

Change-Id: Ie7eee83fba9320d52240166371fe0c757dbdce49
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-21 09:31:44 +00:00
Kyösti Mälkki cb3e16f287 AMD fam10: Remove HAVE_ACPI_RESUME support
Change-Id: I62bbba8cfe515b3cae413582ff8d062a20e6741b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/15474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-21 09:29:46 +00:00
Usha P 5e59a82c27 soc/intel/common: Set controller state to active in uart init
Set the controller state to D0 during the uart init sequence, this
ensures the controller is up and active.

One more argument "const struct device *dev" has been added
to uart_lpss_init function.

BUG=b:135941367
TEST=Verify no timeouts seen during UART controller enumeration
     sequence in CML, ICL and APL platforms

Change-Id: Ie91b502a38d1a40a3dea3711b015b7a5b7ede2db
Signed-off-by: Usha P <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34810
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-21 09:28:46 +00:00
Tristan Shieh 4b5eefa675 mediatek/mt8183: Enlarge PRERAM_CBFS_CACHE region
Enlarge PRERAM_CBFS_CACHE region from (16K - 4) to (48K - 4) bytes to
decompress and load more data from CBFS in romstage.

BUG=b:134351649
BRANCH=none
TEST=emerge-kukui coreboot

Change-Id: Idc23a67c886718e910ca3c50468e5793f19c8d66
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34896
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-21 09:28:29 +00:00
Tristan Shieh 526d840b13 mediatek/mt8183: Overlap decompressor, verstage and romstage
Since SRAM space is too small to fit all needed features, enable
VBOOT_RETURN_FROM_VERSTAGE and overlap decompressor, verstage and
romstage to gain more space.

BUG=b:134351649
BRANCH=none
TEST=emerge-kukui coreboot

Change-Id: Ibe336cf93b01fa2ea57b4c2e0a89685424878c91
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34871
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-21 09:28:13 +00:00
Yu-Ping Wu 4b3047833f mediatek: Use GPIO based SPI CS
Some boards (e.g., Kukui) need GPIO based CS for SPI0. This patch
changes the pinmux and binds the pins to the correponding SPIs.

When using GPIO based SPI CS, we need to manually make CS log/high
before/after SPI transactions.

BUG=b:132311067
BRANCH=none
TEST=Verified that b/132311067 is irreproducible

Change-Id: I61653fb19242b6ee6be9a45545a8b66e5c9c7cad
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-21 09:27:39 +00:00