Commit graph

119 commits

Author SHA1 Message Date
Furquan Shaikh
c948746c21 google/reef: Update chromeos.fmd file
1. Mark 256KiB at end of BIOS region as unusable BIOS region is
memory-mapped just below 4GiB, however last 256KiB is unusable. Mark it
accordingly in fmd file.
2. Use up holes in RW region for RW_A and RW_B.
3. Fill up holes in RO with UNUSED regions.

BUG=chrome-os-partner:54672

Change-Id: I5facc566bb70d950522e12228b0631ddf00ac63d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15313
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-23 20:56:52 +02:00
Furquan Shaikh
0e820ce745 mainboard: Remove use of IFD_BIOS_START/IFD_BIOS_END
BUG=chrome-os-partner:54563

Change-Id: If07710333cbb84ce70d6d4fa40602a74c898c08a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15293
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-06-22 22:21:13 +02:00
Furquan Shaikh
e0667f7b54 google/reef: Keep ISH enabled for now
Disabling ISH causes resets in FSP which leads to hang. This should be
fixed in a later stepping. Until then keep ISH enabled.

BUG=chrome-os-partner:54033

Change-Id: Id9cb276eed8d027ab6d2e81a5ec962bc730c1ff5
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15142
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-06-21 22:01:55 +02:00
Freddy Paul
8200761912 google/reef: Add ACPI code for trackpad
This patch enlists ELAN trackpad on I2C4 for reef board.

BUG=None
TEST=Build and boot to OS.
     Ensure ELAN trackpad is working with ELAN trackpad driver enabled
     in kernel.

Change-Id: I788600f16dea9fac0e089cb82ccfc38a960157f9
Signed-off-by: Freddy Paul <freddy.paul@intel.com>
Reviewed-on: https://review.coreboot.org/15213
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-21 17:10:12 +02:00
Zhao, Lijian
e813c15443 google/reef: Update EMMC DLL setting in all mode
Update tuned DLL setting on all other mode, including SDR12
SDR25 and DDR50.

Change-Id: I1eb85ac6080fd78f63816d3fa9ef482484bd9f94
Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/15210
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-17 21:30:45 +02:00
Furquan Shaikh
4b373ca8a0 google/reef: Add NVRAM and LEGACY sections to chromeos.fmd
Now that the flash size is increased to 16MiB, add RW_NVRAM and
RW_LEGACY sections to chromeos.fmd file.

BUG=chrome-os-partner:54390

Change-Id: I6c79d35295c4bc774f05f8045ac920474d7a791f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15192
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-16 08:15:06 +02:00
Furquan Shaikh
2c4a60da35 google/reef: Update flash size to 16MiB
Use entire 16MiB flash size on reef. Adjust SIGN_CSE region
accordingly.

BUG=chrome-os-partner:54390

Change-Id: I94de509bdb2aa94625814123bf4d9758bfa37fc9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15191
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-16 08:14:39 +02:00
Furquan Shaikh
579fdb4910 google/reef: Correct use of globalnvs.asl
Use the correct globalnvs.asl from apollolake.

BUG=chrome-os-partner:54342

Change-Id: I1a5b8f61c540bdb2668b532f032350d8e4d48010
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15178
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-14 18:26:12 +02:00
Zhao, Lijian
e9cf848dad google/reef: Update EMMC DLL settings
Update EMMC DLL setting for reef board, after that system can
boot up into EMMC successfully.

BUG=chrome-os-partner:54228
TEST=Boot up into EMMC and check with Rootdev

Change-Id: I614cd624dce9069c5565599a955f87906bcea53b
Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/15156
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-14 18:05:47 +02:00
Jagadish Krishnamoorthy
00f21c7724 mainboard/google/reef: Configure sd card pins
Since the sd card cmd, data, cd lines are configured
as native mode, allow the native controller to control
the termination.
Configure SDCARD_CLK_FB which is used for calibrating the
timing of the actual clock buffer.

BUG==chrome-os-partner:53747
TEST=verify sd card detection

Change-Id: I56611826afb4fb32fefa7f1e4ba19ca4f30ba578
Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/348377
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15096
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
2016-06-08 16:11:54 +02:00
Shaunak Saha
f6118c62a4 google/reef: Add asl code to enable google ChromeEC
This patch adds asl code to include support for Google ChromeEC.
We need this to show the battery icon and notifications like charger
connect/disconnect etc.

BUG = 53096
TEST = Plug/Unplug AC Adapter multiple times and make sure the battery
       connected is charging properly.

Change-Id: I06f48eda894418514c8ed0136500fff0efd12a35
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15069
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-06-07 18:31:20 +02:00
Furquan Shaikh
ab90f96ba5 google/reef: Select UART_FOR_CONSOLE for reef
Change-Id: I714af8ab552dc1923a1b64e0c502d6c7b96dd444
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15044
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-02 17:21:17 +02:00
Furquan Shaikh
989842c972 mainboard/google/reef: Add IFWI region to chromeos.fmd
IFWI region holds different components required for booting including
CSE firmware, PMC firmware, CPU microcode as well as the bootblock. Add
section for IFWI in chromeos.fmd

Change-Id: Ic97980ff222ad7cbd7a2970417b79150256a7a16
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15000
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-01 17:17:15 +02:00
Furquan Shaikh
97d56fa1a2 reef: Remove si-all region from chromeos.fmd
This matches the change in depthcharge fmap.dts to remove si-all
region and mark si-desc as ifd.

CQ-DEPEND=CL:347986
BUG=chrome-os-partner:53689
BRANCH=None
TEST=Compiles successfully

Change-Id: Ic7ed94fcdfb9a79bd6ceb960830f67678b0291b6
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/14990
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-30 23:50:06 +02:00
Aaron Durbin
07dd474d65 mainboard/google/reef: increase BIOS region size
An updated descriptor expands the BIOS region while descreasing
the 'device expansion region' utilized by the CSE. Update the
end region marker to reflect this new size as well as the
chromeos.fmd file which needs to be adjusted for logical boot
parition 2 requirement which resides halfway through the BIOS
region. The GBB was moved and shunk to accommodate the change.

Change-Id: I7baa5282d7c608af648b5773c4dfa123060a6e45
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14974
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
2016-05-27 19:55:30 +02:00
Furquan Shaikh
2b56ba5a4f google/reef: Sync chromeos.fmd with fmap.dts and fix offsets
CQ-DEPEND=CL:347460
BUG=chrome-os-partner:53689
BRANCH=None
TEST="emerge-reef chromeos-bootimage" completes without error

Change-Id: Ic954e29628423937604772a8d2d0414954e6ba3e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/347441
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/14975
Tested-by: build bot (Jenkins)
2016-05-27 19:54:43 +02:00
Aaron Durbin
7a3edb6f27 mainboard/google/reef: support verstage
The chromeos.c suport needs to be linked into verstage so it will
link.

Change-Id: If85e232a3721443edfbbd278b32f72302f13f3a8
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14973
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-27 19:54:06 +02:00
Aaron Durbin
451b1e0b9d mainboard/google/reef: add first pass of full pad configuration
This is an initial stab of configuring the reef pads.

Change-Id: I8d8060745af6fbada268c6c6f3492b985ddf9eb8
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14831
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Tested-by: build bot (Jenkins)
2016-05-17 06:18:17 +02:00
Aaron Durbin
e065bb43d7 mainboard/google: add reef reference board
This adds the initial scaffolding for the reef reference board.
One big thing missing is the GPIO configuration.

Change-Id: I8e2d275df296bb397bb33dbd0c66fc87c82ff10f
Signed-off-by: Aaron Durbni <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14798
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-13 22:38:53 +02:00