- Add missing entry for the NIC:
device pci 0f.0 on end # Ethernet (onboard)
- Drop the following lines:
register "com1" = "{115200}"
register "com2" = "{38400}"
Those entries hardcode the BAUD rate (as far as I can tell, please
correct me if I'm wrong). We don't want that -- instead the config option
TTYS0_BAUD in Options.lb should be used(?) I verified that dropping those
lines will not break serial output (COM1, 115200, 8n1).
- Enable IDE (PCI device 00:12.2) and add the following register lines
to tell the CS5530 code to actually enable IDE channel 0:
register "ide0_enable" = "1"
register "ide1_enable" = "0" # Not available/needed on this board
Tested with a 2.5" hard drive and FILO, works fine.
- Enable USB (PCI device 00:13.0), not sure why it was commented.
- Enable COM2 as it's used by the smartcard reader.
- Add CONFIG_COMPRESSED_PAYLOAD_LZMA to Options.lb, in order to fix
abuild for this board.
- Add some more comments.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2896 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
making the output of "make -s" finally usable.. (still trivial, doesn't
change any logic or remove any code)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2894 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
make them const before putting them into the read-only segment...
(trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2892 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
rodata.pci_driver" warnings are coming from? We were packing those
structures into a read-only segment, but forgot to mark them const.
Despite its size, this is a fairly trivial patch created by a simple
search/replace
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2891 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
assumes a 1MB rom chip.
Hence the default position for the VGA bios should also assume a 1MB rom chip,
not a 512KB chip.
Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2887 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2883 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2882 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
since it is still our most wide-spread codebase.
The patch is pretty trivial, and nobody except Torsten even looked at
it in a week, so....
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2880 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
serious issue, so I am self-acking.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2879 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
days on a function named pll_reset that, on exit, says "Done
cpuRegInit", and which, in turn, made me think it was a lot farther
along that it was.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2878 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
status register instead.
This has been tested by Harald Gutmann <harald.gutmann@gmx.net> with a
MX25L4005 chip.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2876 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
chip the code was tested and verified with is the Macronix MX25L4005,
but other chips should work as well.
Timeouts are still hardcoded to data sheet maxima, but the status
register checking code is already there.
Thanks to Harald Gutmann for the initial code on which this is loosely
based.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2874 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
the --dump option, it just means lots of additional work for no gain, IMO.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2872 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
We often want to know the exact version number of superiotool which
was used to gather a certain output/dump.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2871 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
case of keyboard failure (the keyboard initialization was never hit).
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2869 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This has not been working at all until now. With this fix, keyboard,
mouse, parallel port, and the Super I/O sensors work fine (tested
on actual hardware).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2867 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Install binary in /usr/sbin (not /usr/bin), as it's a root-only tool.
- Rename manpage from flashrom.1 to flashrom.8, as section 8 contains
"System administration commands (usually only for root)".
- Actually install the manpage upon 'make install'.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2866 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Michael van der Kolff <mvanderkolff@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2864 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
has a slightly different format than that of the W83697UF/UG so we have
to hack around it a bit.
This patch has been verified to work on real hardware by
Idwer Vollering <idwer_v@hotmail.com> on IRC (thanks!).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2861 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
replacing it with a minimal, but working, framework which will be expanded.
Drop a bunch of useless and duplicated files, add missing license headers.
I'm self-acking it this time, the diff is a huge unreadable mess and the old
code is broken anyway...
This code is tested to build fine, and can boot a Linux kernel up to a
login-prompt via FILO (IDE). This is verified on actual hardware.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2859 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Move SPI code out of board_enable.c where it started its life. The SPI
chip finding and SPI chip accessor code is moved as well. This can be
split later if we feel like it.
The non-use of svn cp is intentional because the only history we'd have
to preserve are a few commits which were early prototypes of chip
identification code. For those who intend to look at that history, they
can look at board_enable.c revision 2853.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2858 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
chip finding and SPI chip accessor code is moved as well. This can be
split later if we feel like it.
The non-use of svn cp is intentional because the only history we'd have
to preserve are a few commits which were early prototypes of chip
identification code. For those who intend to look at that history, they
can look at board_enable.c revision 2853.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2857 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Joseph Smith <joe@smittys.pointclark.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2856 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
of the Winbond chips from being detected (trivial fix).
This is verified on real hardware and works fine now.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2855 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Without this bugfix, the resource for the PCI/ISA video memory at
0xa0000 - 0xbffff is too big, i.e. it goes up to 0xcffff instead of
just 0xbffff as it should.
Here's the diff from two runs of the tool from
http://www.linuxbios.org/pipermail/linuxbios/2007-June/022449.html
on the MSI MS-7260 (K9N Neo), with and without the bugfix. After applying,
the resource size is correct again.
--- dumpres_lb_pci_vgacard_without_resfix.txt
+++ dumpres_lb_pci_vgacard_with_resfix.txt
@@ -11,7 +11,7 @@
MMIO map: #2 0x0000000000 - 0x000000ffff Access: / Dstnode:0 DstLink 0
MMIO map: #3 0x0000000000 - 0x000000ffff Access: / Dstnode:0 DstLink 0
MMIO map: #4 0x0000000000 - 0x000000ffff Access: / Dstnode:0 DstLink 0
-MMIO map: #5 0x00000a0000 - 0x00000cffff Access: R/W Dstnode:0 DstLink 0
+MMIO map: #5 0x00000a0000 - 0x00000bffff Access: R/W Dstnode:0 DstLink 0
MMIO map: #6 0x00fc000000 - 0x00fd1fffff Access: R/W Dstnode:0 DstLink 0
MMIO map: #7 0x00fd200000 - 0x00fd1fffff Access: R/W Dstnode:0 DstLink 0
MMIO map: #0 0x000000 - 0x003fff Access: R/W ISA VGA Dstnode:0 DstLink 0
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2853 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
use that feature in order to not waste RAM.
Also, add missing CONFIG_VIDEO_MB for the eaglelion/5bcm, which should
fix the build for that board.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2848 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Uwe Hermann