This function name clashes with cbfs_walk() in the new commonlib CBFS
stack, so rename it to cbfs_legacy_walk(). While we could replace it
with the new commonlib implementation, it still has support for certain
features in the deprecated pre-FMAP CBFSes (such as non-standard header
alignment), which are needed to handle old files but probably not
something we'd want to burden the commonlib implementation with. So
until we decide to deprecate support for those files from cbfstool as
well, it seems easier to just keep the existing implementation here.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I37c7e7aa9a206372817d8d0b8f66d72bafb4f346
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch reduces some code duplication in cbfstool by switching it to
use the CBFS data structure definitions in commonlib rather than its own
private copy. In addition, replace a few custom helpers related to hash
algorithms with the official vboot APIs of the same purpose.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I22eae1bcd76d85fff17749617cfe4f1de55603f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Looks like the option is generally not compatible with
garbage collections.
Nothing gets inlined, for example is_smp_boot() no longer
evaluates to constant false and thus the symbols from
secondary.S would need to be present for the build to pass
even if we set SMP=n.
Also the addresses of relocatable ramstage are currently
not normalised on the logs, so util/genprof would be unable
dress those.
Change-Id: I0b6f310e15e6f4992cd054d288903fea8390e5cf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45757
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The template for overridetree.cb includes HeciEnabled, which has
been removed from the CNL config struct, so remove it from the
overridetree.
BUG=b:174360951
TEST=`new_variant_fulltest.sh puff` succeeds
Signed-off-by: Paul Fagerburg <pfagerburg@google.com>
Change-Id: I87f67c53cc75d9ddd40b4960739180a95de6ecd6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Add MT53D512M64D4NW-046 WT:F memory part to LP4x global list of
available LP4x parts and to the global JSON file containing LP4x parts
and their characteristics.
BUG=b:172993397
TEST=none
Change-Id: I09c6eab640c169dbdb451964967d14a31e314496
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Print whether the SOC supports TME/MKTME. If the SOC supports the
feature, print the status of enable and lock bit from TME_ACTIVATE
MSR. -t option prints this status.
Sample output:
If TME/MKTME is supported:
============= Dumping INTEL TME/MKTME status =============
TME supported : YES
TME locked : YES
TME enabled : YES
====================================================
If TME/MKTME is not supported:
============= Dumping INTEL TME status =============
TME supported : NO
====================================================
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Change-Id: I584ac4b045ba80998d454283e02d3f28ef45692d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Our current cbfstool has always added a compression attribute to the
CBFS file header for all files that used the cbfstool_convert_raw()
function (basically anything other than a stage or payload), even if the
compression type was NONE. This was likely some sort of oversight, since
coreboot CBFS reading code has always accepted the absence of a
compression attribute to mean "no compression". This patch fixes the
behavior to avoid adding the attribute in these cases.
Change-Id: Ic4a41152db9df66376fa26096d6f3a53baea51de
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
- Update url for docker install instructions.
- Update docker-cleanall target to require verification.
- Update docker-jenkins-attach target to check for docker and
use docker variable.
- Update spaces to tabs in the docs targets.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ic1e1a545024fe1fdc37d7d8c7e6f54f124d1697b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47342
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
For whatever reason, I've had buildgcc fail to download packages a
number of times. Adding 2 additional retries before failing helps
with that problem.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I060eaa5a0da955436169e2199c1c62044dcfd5ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Changes (https://nasm.us/doc/nasmdocc.html):
Version 2.15.05:
Correct %ifid $ and %ifid $$ being treated as true.
Add --reproducible option to suppress NASM version numbers and
timestamps in output files.
Version 2.15.04:
Correct the encoding of the ENQCMDS and TILELOADT1 instructions.
Fix case where the COFF backend (the coff, win32 and win64 output
formats) would add padding bytes in the middle of a section if a
SECTION/SEGMENT directive was provided which repeated an
ALIGN= attribute. This neither matched legacy behavior, other
backends, or user expectations.
Fix SSE instructions not being recognized with an explicit memory
operation size (e.g. movsd qword [eax],xmm0).
Change-Id: I3f9aa8e743f2dc50fce1ce68718c0ae17209a509
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44694
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
MR0 may not always be programmed in the training result registers. Thus,
do not rely on its values. Also account for per-channel differences.
Change-Id: Iaf3b545ea55735b46caf1bd62d5859f2b3efa159
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This field is only 4 bits wide.
Change-Id: I2cb746e98176d58fc5be423e18babdaa8801b096
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
In order to allow override trees to hide/unhide a device copy
the hidden state to the base device. This allows a sequence
of states like:
chipset.cb: mark device 'off' by default
devicetree.cb: mark device 'hidden' (to skip resource allocation)
overridetree.cb: mark device 'on' for device present on a variant
BUG=b:159143739
BRANCH=volteer
TEST=build volteer variants with TCSS RP0 either hidden or on
and check the resulting static.c to see if the hidden bit is
set appropriately.
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: Iebe5f6d2fd93fbcc4329875565c2ebf4823da59b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47197
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds the following memory parts to LP4x global list of
available LP4x parts and to the global JSON file containing LP4x parts
and their characteristics.
1. H9HCNNNCRMBLPR-NEE
2. H9HCNNNFBMBLPR-NEE
3. MT53D1G64D4NW-046 WT:A
BUG=b:172751925,b:172781673,b:172782100,b:172781562
TEST=cd <path_to_coreboot_src>/util/spd_tools/lp4x &&
./gen_spd <path_to_coreboot_src>/src/soc/intel/tigerlake/spd \
global_lp4x_mem_parts.json.txt "TGL"
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I37702770f707fe078920694468552c5db59c478f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47350
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The compress and uncompress options don't have arguments and shouldn't
consume the next token. So replace required_argument with no_argument
for the two options.
Change-Id: Ib9b190f2cf606109f82a65d00327871d6ffb7082
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Both the help and the maxsize option had the same short option character
assigned. Change the short option for maxsize to m to fix this and to
make it consistent with the rest of the code.
Change-Id: Icac1a7d4906345c37a5c7bed2b4995fea25f860e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Work on this SoC was abandoned and never finished. It's not really
usable in its current state, so let's get rid of it.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I23453e3e47ac336ab61687004470e5e79172cafe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47428
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Due to the phony dependency to check for openssl, vboot-futility
was always rebuilt, and because it was newer than coreboot-futility,
it was always copied over.
Do that in parallel often enough and you run into race conditions,
as we did on our builders. Mark check-openssl-presence as order-only
dependency so that it's executed (and can bail out) but doesn't force
regeneration of vboot-futility.
Change-Id: Ib7fb798096d423d6b6cba5d199e12fe5917c3b41
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add the missing special function gpio pad groups for CNL-LP.
The groups and names are documented in the PCH EDS, in Linux
(linux/drivers/pinctrl/intel/pinctrl-cannonlake.c) and other places.
Also, see soc/intel/tigerlake for reference.
Change-Id: I0509552da6ffad395c2b89df1676e1903c783695
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add the missing special function gpio pad groups for CNL-H.
The groups and names are documented in the PCH EDS, in Linux
(linux/drivers/pinctrl/intel/pinctrl-cannonlake.c) and other places.
Also, see soc/intel/tigerlake for reference.
Change-Id: Ib83aeef9f4b6aa174e61ccbd87fb7b6450ed773b
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add the missing native functions for special gpio pads for CNL-H,
which are documented in the PCH EDS and other places.
Also, see soc/intel/tigerlake for reference.
Change-Id: I71339d66362d29806c91375c214e9fb84c989201
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The names of the GPIO_RSVD_* are documented in the PCH EDS, in Linux
(linux/drivers/pinctrl/intel/pinctrl-cannonlake.c) and other places.
Also, see soc/intel/tigerlake for reference.
Change-Id: Ifd6cabb646000c8dff695c5c4f7196b2779f1430
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add the missing native functions for special gpio pads for CNL-LP,
which are documented in the PCH EDS and other places.
Also, see soc/intel/tigerlake for reference.
Change-Id: Iedb726aa3afdbbbedafb67f6b7668bf591c2b9b4
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The names of the GPIO_RSVD_* are documented in the PCH EDS, in Linux
(linux/drivers/pinctrl/intel/pinctrl-cannonlake.c) and other places.
Also, see soc/intel/tigerlake for reference.
Change-Id: I86c7159d9f48560c41efdfe49f162aef00499d13
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This config tries to mimic the actual devices of a mainboard
with Intel's Q35 chipset. It provides a much better base to
test coreboot (e.g. its allocator) and payloads.
Change-Id: Id465016e37ee75628a55b9da68facb4ae0efe822
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add some mechanics to automatically have a `qemu` make target for
supported configurations. So with a QEMU target selected in Kconfig,
one would ideally only have to run `make qemu` to test things.
There are some notable variables that can be set or adapted in
`Makefile.inc` files, the make command line or the environment.
Primarily for `Makefile.inc` use:
QEMU-y the QEMU executable
QEMU_CFG-y a QEMU config that sets the available default devices,
used to run more comprehensive tests by default,
e.g. many more PCI devices
For general use:
QEMU_ARGS additional command line arguments (default: -serial stdio)
QEMU_EXTRA_CFGS additional config files that can add devices
QEMU_CFG_ARGS gathers config file related arguments,
can be used to override a default config (QEMU_CFG-y)
Examples:
$ # Run coreboot's default config with additional command line args
$ make qemu QEMU_ARGS="-cdrom site-local/grml64-small_2018.12.iso"
$ # Force QEMU's built-in config
$ make qemu QEMU_CFG_ARGS=
Change-Id: I658f86e05df416ae09be6d432f9a80f7f71f9f75
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
It slightly helps debugging issues when you know what to look out for.
Change-Id: I21eafaf8291701316aa920e458ba74535121b0a1
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
We are implementing a mechanism in coreboot to update CSME firmware,
this requires coreboot to be able to read CSME region. Exposing the
CSME data is not an issue since the data stored by CSE is all encrypted.
This patch provides a command line option "-r" which will enable read
access to CSME region when locking.
Without this change, locking SPI regions using ifdtool will block BIOS
access to read/access CSME. This will cause failure since BIOS can't
read basic information such as CSME version.
TEST=Flashrom returns success while erasing the SI_ME region.
After rebooting the DUT, DUT boots into OS without any issues on
Drawlat EVT.
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I1d9a8e17fba19b717453476fbcb7bcf95b278abe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
These were originally ignored only inside util/ but these files
shouldn't be tracked anywhere.
Change-Id: Ie0846bd8bdd6e52f420f9dd2e72a8a922102ff90
Signed-off-by: Patrick Georgi <patrick@georgi.software>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
We all knew this was coming, 32 bits is never enough. Doing this early
so that it doesn't affect too much code yet. Take care of every usage of
fw_config throughout the codebase so the conversion is all done at once.
BUG=b:169668368
TEST=Hacked up this code to OR 0x1_000_0000 with CBI-sourced FW_CONFIG
and verify the console print contained that bit.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I6f2065d347eafa0ef7b346caeabdc3b626402092
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45939
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To verify the consistency, see if timeless builds with and without
this patch result in identical coreboot.rom files.
BUG=b:154032833
TEST=Build & boot on mandolin
Change-Id: Icae73d0730106aab687486e555ba947796e5e757
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
core-ec will need it.
Change-Id: Id7d677a6f92ce266f893372a2540d77abb613707
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
There's no need for the global list of files to ignore, so use git's
ability to work with more local configuration.
Change-Id: I50882e6756cbc0fdfd899353cc23962544690fb3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46879
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This will let you at least dump / add these regions.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: I195ba5e93823603e712cd16cecbb48141302bed6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Julius Werner