Commit graph

11 commits

Author SHA1 Message Date
Duncan Laurie
2661a9f517 google/eve: Use rt5514 instead of 4ch DMIC
On this platform the DMICs are connected to the rt5514 DSP instead
of directly connected to the SOC.  Use the new rt5514 NHLT blob
instead of the 4ch DMIC blob and add the required I2C and SPI
entries in devicetree so this can get probed properly.

BUG=b:35585307
BRANCH=none
TEST=build and boot on Eve P1 and check for rt5514 driver enumerated
by the kernel

Change-Id: I0f2cb532771ee1857df7f33c52a96acf96dc1f54
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18817
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-15 18:32:40 +01:00
Furquan Shaikh
5360c7ef94 drivers/i2c: Use I2C HID driver for wacom devices
Wacom I2C driver does the same thing as I2C HID driver, other than
defining macros for Wacom HID. Instead of maintaining two separate
drivers providing the same functionality, update all wacom devices to
use generic I2C HID driver.

BUG=None
BRANCH=None
TEST=Verified that ACPI nodes for wacom devices are unchanged.

Change-Id: Ibb3226d1f3934f5c3c5d98b939756775d11b792c
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18401
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-02-20 21:41:34 +01:00
Duncan Laurie
5492bfb55c google/eve: Add audio devices
Add the audio devices to Eve mainboard:

- Describe Maxim 98927 speaker amps and RT5663 headphone codec
in ACPI so they can be enumerated by the OS.

- Supply NHLT binaries for MAX98927, RT5663, and DMIC_4CH.

BUG=chrome-os-partner:61009
TEST=manual testing on Eve P1 with updated kernel to ensure that
both speakers and headset are functional.  DMIC support is
is still being worked on and is not yet functional.

Change-Id: I5243e35d159a0ed15c6004e94ba5a50b28cff0a9
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18398
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
2017-02-20 20:51:14 +01:00
Furquan Shaikh
97535558f1 mainboard/{google,intel}: Change config option selection
Change config option selection from "config xyz default y" to "select
xyz" if the config option has no dependencies.

BUG=None
BRANCH=None
TEST=Verified that config option selection remains unchanged.

Change-Id: I259ae40623b7f4d5589e2caa0988419ba4fefda4
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18400
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-02-20 05:08:27 +01:00
Rizwan Qureshi
ceccb6ba53 mainboard/eve: select SOC_INTEL_KABYLAKE
eve is based on Kabylake SoC hence select the appropriate
config.

Change-Id: I756dda5a1924e83a02ac1cebb1907884f436a13f
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/18314
Tested-by: build bot (Jenkins)
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-02-17 19:02:47 +01:00
Furquan Shaikh
231c198e2c mainboard/google/eve: Generate FPC device using SPI SSDT generator
Use the newly added SPI SSDT generator for adding FPC device.

BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles successfully. Verified that the SSDT entry matches the
entry in mainboard.asl

Change-Id: I1b3c33f2b4337735a9725dd4eb6193b2455962d7
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18343
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-02-16 08:42:38 +01:00
Duncan Laurie
e00365217c google/eve: Enable separate recovery MRC cache
In order to get quick boot speeds into recovery enable the
feature that allows for a separate recovery MRC cache.

This requires shuffling the FMAP around a bit in order to
provide another region for the recovery MRC cache.  To make
that shuffling easier, group the RW components into another
sub-region so it can use relative addresses.

BUG=chrome-os-partner:58666
TEST=manual testing on eve: check that recovery uses the MRC
cache, and that normal mode does too.  Check that if cache is
retrained in recovery mode it is also retrained in normal mode.
Also check that events show up in the log when retrain happens.

Change-Id: I6a9507eb0b919b3af2752e2499904cc62509c06a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18199
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-22 19:25:04 +01:00
Duncan Laurie
2d14021279 google/eve: Enable touch devices
Enable the actual touch devices to be probed by the kernel
and remove the placeholder devices that I put in before
and were used for initial bringup.

BUG=chrome-os-partner:58666
TEST=tested on eve

Change-Id: I7fc6f9da83b1abbae6dd069f759b220d59153d1c
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17896
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-16 17:00:28 +01:00
Kyösti Mälkki
bac0fad408 Remove explicit select MMCONF_SUPPORT
Make MMCONF_SUPPORT selected with MMCONF_SUPPORT_DEFAULT.

Platforms that remain to have explicit MMCONF_SUPPORT are
ones that should be converted.

Change-Id: Iba8824f46842607fb1508aa7d057f8cbf1cd6397
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17527
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-22 04:15:11 +01:00
Furquan Shaikh
cd2afc0df0 google/chromeec: Add common infrastructure for boot-mode switches
Instead of defining the same functions for reading/clearing boot-mode
switches from EC in every mainboard, add a common infrastructure to
enable common functions for handling boot-mode switches if
GOOGLE_CHROMEEC is being used.

Only boards that were not moved to this new infrastructure are those
that do not use GOOGLE_CHROMEEC or which rely on some mainboard specific
mechanism for reading boot-mode switches.

BUG=None
BRANCH=None
TEST=abuild compiles all boards successfully with and without ChromeOS
option.

Change-Id: I267aadea9e616464563df04b51a668b877f0d578
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17449
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
2016-11-18 04:01:59 +01:00
Duncan Laurie
81485d2763 google/eve: Add new board
Add the eve board files using kabylake and FSP 2.0.

BUG=chrome-os-partner:58666
TEST=build and boot on eve board

Change-Id: I7ca71fe052608d710ee65d078df7af7b55d382bc
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17177
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
2016-11-01 22:54:25 +01:00