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59 Commits

Author SHA1 Message Date
Li-Ta Lo db7f47cbbf Change PCI_BRIDGE_CONTROL to PCI_BRIDGE_CTL_VGA 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1324 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2004-01-08 21:15:49 +00:00
Eric Biederman 83b991afff - O2, enums, and switch statements work in romcc 
- Support for compiling romcc on non x86 platforms
  - new romc options -msse and -mmmx for specifying extra registers to use
  - Bug fixes to device the device disable/enable framework and an amd8111 implementation
  - Move the link specification to the chip specification instead of the path
  - Allow specifying devices with internal bridges.
  - Initial via epia support
 - Opteron errata fixes


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1200 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2003-10-11 06:20:25 +00:00
Ronald G. Minnich 99dcf231f4 The epia now works. 
Now to fix the ram ...


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1159 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2003-09-30 02:16:47 +00:00
Eric Biederman e9a271e32c - Major update of the dynamic device tree so it can handle 
* subtractive resources
  * merging with the static device tree
  * more device types than just pci
- The piece to watch out for is the new enable_resources method that was needed in all of the drivers


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1096 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2003-09-02 03:36:25 +00:00
Eric Biederman bbb6d1020f - Fix poor resource allocation estimate. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1066 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2003-08-04 19:54:48 +00:00
Eric Biederman 2c018fba95 - First pass at s2880 support. 
- SMP cleanups (remove SMP only use CONFIG_SMP)
- Minor tweaks to romcc to keep it from taking forever compiling
- failover fixes
- Get a good implementation of k8_cpufixup and sizeram for the opteron


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@998 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2003-07-21 20:13:45 +00:00
Eric Biederman 7a5416af95 - Modify the freebios tree so the pci config space api is mostly in sync between 
code that runs without ram and code that runs with ram.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@869 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2003-06-12 19:23:51 +00:00
Eric Biederman 5899fd82aa - Small step forward Linux boots and almost works... 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@795 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2003-04-24 06:25:08 +00:00
Eric Biederman 8ca8d7665d - Initial checkin of the freebios2 tree 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@784 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2003-04-22 19:02:15 +00:00