Commit Graph

9889 Commits

Author SHA1 Message Date
Vladimir Serbinenko 39268299c0 linutop: Add Linutop-1 as a clone of artecgroup/dbe61
Change-Id: I69e99e2a1bf9b890281caaf0633f91850d923241
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4747
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-19 19:10:31 +01:00
Vladimir Serbinenko 08c372f460 boardstatus: Do not error out on unknown CPU/northbridge
On bot, stderr is unmonitored, so it make no sense to stop with an error.
Instead use some sensible guesses.

Change-Id: I6292e9fbf446b751471b95f86e7515c6680bddf3
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4748
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-19 19:09:50 +01:00
Vladimir Serbinenko c9babb278f nvramcui: Trim values when setting.
Values get space-padded by curses and then enum search fails to match them.
Rtrim to compensate for curses.

Change-Id: Iecf095f21cfade9425eaa039b67625615eb80481
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4692
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
2014-01-19 15:09:29 +01:00
Vladimir Serbinenko 571bec726c libpayload/lpgcc: Add curses include path.
Without it payloads that need curses fail to build.

Change-Id: I4533238b547e4c2d9e0778fb7d314db35a9559df
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4689
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2014-01-19 15:05:20 +01:00
Vladimir Serbinenko 2a0fc9fbb4 boardstatus: Drop v4 mention of coreboot version.
Change-Id: I5cf34e14f6e11c03822a6ce6226365c76e0f6875
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4742
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-19 12:42:39 +01:00
Vladimir Serbinenko 7ea00155b2 libpayload/options: Fix out of array read.
It resulted in garbage in upper bytes of numeric options.

Change-Id: I5e5d8b770ed93c7e8a1756a5ce32444b6a045bac
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4691
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2014-01-19 11:51:23 +01:00
Patrick Georgi fd5b370437 libpayload: Bring keyboard_wait_write() back
Code is using it...

Change-Id: I6894b45cbbf70c8e7ce37ce18d93cadf0ea9fbfc
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/4649
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2014-01-19 11:37:39 +01:00
Vladimir Serbinenko 5fb48a85dc boardstatus: Accept only hex digits for AMD family number.
Change-Id: Ia13e54f35215d07d93f93887eef5aeb91ffb874d
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4741
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-01-19 04:04:50 +01:00
Vladimir Serbinenko aa998bb480 boardstatus: Skip SKI_ISA_DMA_INIT configs.
Change-Id: I10872c31baa0d73ce55d1738a0643fda2555c62e
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4740
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-01-19 04:04:41 +01:00
Vladimir Serbinenko 047c10c0f8 boardstatus: Add new category "sbc".
Change-Id: I8a7bf265ebb30dd5997f93729a0329e74f463a23
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4739
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-01-19 03:20:08 +01:00
Vladimir Serbinenko 14a703045d boardstatus: Add category "emulation".
Change-Id: If9d26b9e4cb1895452316c9cf2e8c75a01cfd7c2
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4738
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-01-19 03:17:18 +01:00
Vladimir Serbinenko 13cd4907f2 board_info.txt: Remove some needless name overrides.
Overrides were to have names in line with wiki but names derived from the
tree are better in some cases.

Change-Id: Ic805ba9a3b9c7f926dc9ef27f8673f2c18e9af34
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4737
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-01-19 03:09:49 +01:00
Vladimir Serbinenko 2e71e55d33 board_info.txt: Change iei/kino's link to web.archive.org.
Original link is dead.

Change-Id: I56e975ee411f7290c12aad501f490ccc5dedaf05
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4736
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-19 03:09:25 +01:00
Vladimir Serbinenko 1af25246a9 board_info.txt: declare chromebooks as laptops.
Change-Id: I4a3ed7e9b6aaec8aba8ffc47eafdbcca31e4c700
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4734
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-01-19 02:57:16 +01:00
Vladimir Serbinenko 9514f5a901 board_info.txt: Categorize various boards
Info supplied by: idwer

Change-Id: I3086e8118a721ded33c578c6c82e20642ef9d776
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4733
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-01-19 02:47:06 +01:00
Vladimir Serbinenko 0fc8ed6318 boardstatus: Remove some needless name overrides.
Overrides were to have names in line with wiki but names derived from the
tree are better in some cases.

Change-Id: Iff3c27db1a4936b03f976c82d872589e41df0c90
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4735
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-19 02:46:54 +01:00
Vladimir Serbinenko 2eaf3b4e3a boardstatus: Handle clones.
Change-Id: I7bfe19eb800729713a549dc0396765a9785e11b1
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4732
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-19 02:18:33 +01:00
Vladimir Serbinenko 03cd8e5fa4 boardstatus: Use Board:$vendor/$board for board pages.
Change-Id: I5249d86188845e1104d25163faa5010b943e707a
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4731
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-19 02:06:17 +01:00
Vladimir Serbinenko acca285973 board-status: Add board_info.txt manually for irregular wiki entries
Based on info from wiki.

Change-Id: Iebd799abe48550c4df55632b8177d845df7d9a7d
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4706
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-19 02:00:35 +01:00
Vladimir Serbinenko 4333071e23 board-status: Add board_info.txt extracted from wiki.
board_info.txt is a file to be used by board-status to add
some useful info to the generated table like flash chip type.
This series is autogenerated from wiki page Supported_Motherboards.

Change-Id: Ie2bda900713ef4883134477163320936c84c34f5
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4701
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-19 01:35:03 +01:00
Vladimir Serbinenko af771885a5 jetway/j7f4k1g2e and jetway/j7f4k1g5d: Add as clones of jetway/j7f2.
Change-Id: I16e027b78dc65538d8f0cd6f5e57bbdfc10b7169
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4729
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-01-19 00:40:32 +01:00
Vladimir Serbinenko 21a2707ea9 boardstatus: Remove support for multiname mobos.
It's ugly and not needed anymore.

Change-Id: I98301c75684813a217c3ca0435a15b6e4ffef558
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4730
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-19 00:37:58 +01:00
Vladimir Serbinenko 2cb9685860 jetway/j7f24: Rename to jetway/j7f2.
Original actually meant j7f[24] which without square brackets
became confusing.  There is no such board as j7f24.

This is a prerequisite to adding j7f4* as cloned boards

Change-Id: Ia7708b13ac4141ef788183c7817fce1366919936
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4728
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-01-19 00:18:05 +01:00
Vladimir Serbinenko fb07108894 via/epia-mii and via/epia-ml: Add as clones of epia-m.
Change-Id: I4f297e7a7332acc6ceda6a99981599e3a372b696
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4727
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-01-19 00:05:57 +01:00
Vladimir Serbinenko f16d9c6bcc iei/rocky-512: Add it as an explicit clone of juki-511p.
Change-Id: I87e2768de6728658a87729998648514824d79fd6
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4726
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-01-18 23:56:37 +01:00
Vladimir Serbinenko e66548d010 A8N-SLI: Add it explicitly as a clone of A8N-E
Change-Id: Ieab7d46177eb92393914f8cb055675df00a9a375
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4723
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-18 23:56:29 +01:00
Vladimir Serbinenko 49fef4b6cb boardstatus: Take default board name from MAINBOARD_PART_NUMBER.
Change-Id: I2f775e8919cfd35bbcf5910a8b25776e833ee100
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4722
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-01-18 22:30:33 +01:00
Vladimir Serbinenko 22210dd95b boardstatus: generate table of all boards with links to latest run
Change-Id: I78f94238d7931c8b41e63174220ec4392108f4ce
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4699
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-18 21:32:36 +01:00
Alexandru Gagniuc 07d881a02d cpu/intel: Remove dummy terminators from microcode blobs
Now that CBFS microcode no longer requires a NULL termination, remove the
dummy terminators from all microcode blobs. This also enables microcode
blobs from different CPU models to be linked in the same
cpu_microcode_blob.bin without the terminators getting in the way.

Change-Id: I25a6454780fd5d56ae7660b0733ac4f8c4d90096
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4506
Tested-by: build bot (Jenkins)
2014-01-16 05:35:28 +01:00
Alexandru Gagniuc 2c38f50b4a cpu/intel: Make all Intel CPUs load microcode from CBFS
The sequence to inject microcode updates is virtually the same for all
Intel CPUs. The same function is used to inject the update in both CBFS
and hardcoded cases, and in both of these cases, the microcode resides in
the ROM. This should be a safe change across the board.

The function which loaded compiled-in microcode is also removed here in
order to prevent it from being used in the future.

The dummy terminators from microcode need to be removed if this change is
to work when generating microcode from several microcode_blob.c files, as
is the case for older socketed CPUs. Removal of dummy terminators is done
in a subsequent patch.

Change-Id: I2cc8220cc4cd4a87aa7fc750e6c60ccdfa9986e9
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4495
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-01-16 05:34:25 +01:00
Vladimir Serbinenko b4c39902ed butterfly: fix compilation with !CHROMEOS
One of arguments to cbfs_get_file_content was missing.

Change-Id: Icb4ef26f18d63c133bc32f1c62a524edee0621ea
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4696
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-16 04:34:30 +01:00
Idwer Vollering c18e52122d AMD Hudson: show POST codes on a PCI device
Show POST codes on a PCI device: implement hudson_pci_port80().
Remove the comments that use pci_locate_device():
using the code found in the comment seems to break booting.

This shares much code with sb600/sb700/sb800,
however the deduplication work needs to be discusses somewhere else
than in this review board.

Tested on an Asus F2A85-M.
The contribution is (C) by Rudolf Marek.

Change-Id: I54fb1dcb0614452c775ed70d867ab44ff263a61a
Author: Rudolf Marek <r.marek@assembler.cz>
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/4559
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-01-15 22:27:21 +01:00
Paul Menzel be8d23a3b5 cpu/amd/model_fxx/powernow_acpi.c: Comment out set but unused variable `Start_vid`
When adding support for PSS object generation for AMD pre Family Fh CPUs
(199c694f) the function `pstates_algorithm` was copied and adapted, but
`Start_vid` is not needed anymore as a static table is used. I’d remove
the variable, but Ron Minnich requested to leave it there for
documentation purposes. So just comment it out.

Change-Id: I3002951d168cade6461941c16d78373c47792e13
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/4036
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-01-15 22:20:20 +01:00
Vladimir Serbinenko 01d06dc67b ROMSIZE: Add option for 12M chips.
On X230 2 real chips (8 + 4) are merged into one virtual 12M chip.

Change-Id: I49c251b1777fc9edccebc4a204b9c4a087bf2a8e
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4688
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-01-15 16:35:53 +01:00
Kyösti Mälkki 78938481eb Intel (sandy/ivy): Avoid calling cbmem_initialize() twice
Delay the copying of MRC cache data from CAR to CBMEM until after
sdram_initialize() returns and cbmem_initialize() completes.
Calling cbmem_initialize() twice would complicate the decision logic
of when CBMEM area needs to be wiped clean.

Change-Id: Ic59e94cb2436293efc47b52f7418f5dbf76c714a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4666
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-01-15 15:33:54 +01:00
Kyösti Mälkki 1e5cacc8f8 google/stout: Add EARLY_CBMEM_INIT
Required for MRC cache and for HAVE_ACPI_RESUME to work.

Change-Id: I7d48b167bd581d7c14ca50bd46e74be0133cecfb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4665
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-01-15 15:31:15 +01:00
Kyösti Mälkki cb08e169cf CBMEM intel: Define get_top_of_ram() once per chipset
Only have one definition of get_top_of_ram() function and compile
it using __SIMPLE_DEVICE__ for both romstage and ramstage.

Implemented like this on intel/northbridge/gm45 already.
This also adds get_top_of_ram() to i945 ramstage.

Change-Id: Ia82cf6e47a4c929223ea3d8f233d606e6f5bf2f1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3993
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-01-15 15:29:52 +01:00
Kyösti Mälkki bbf013c38f nehalem/sandy/ivy/haswell: Enable WRPROT cache for all of flash
CBFS could start from below 4MB, and should be cacheable for the
purpose of early microcode update and CBFS search for romstage file.

Change-Id: Ia2a1c6e5fdcc3201fafc8cf5c841cebbbf0b30c9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4626
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-01-15 15:27:33 +01:00
Kyösti Mälkki 107f72e674 Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR
This change allows Kconfig options ROM_SIZE and CBFS_SIZE to be
set with values that are not power of 2. The region programmed
as WB cacheable will include all of ROM_SIZE.

Side-effects to consider:

Memory region below flash may be tagged WRPROT cacheable. As an
example, with ROM_SIZE of 12 MB, CACHE_ROM_SIZE would be 16 MB.
Since this can overlap CAR, we add an explicit test and fail
on compile should this happen. To work around this problem, one
needs to use CACHE_ROM_SIZE_OVERRIDE in the mainboard Kconfig and
define a smaller region for WB cache.

With this change flash regions outside CBFS are also tagged WRPROT
cacheable. This covers IFD and ME and sections ChromeOS may use.

Change-Id: I5e577900ff7e91606bef6d80033caaed721ce4bf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4625
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-01-15 15:26:48 +01:00
Vladimir Serbinenko 5e73be2a7a sandybridge: Allow skipping mrc.cache
On X230 MRC fails if cache is passed to it. Until better solution is found
do not create mrc.cache

Change-Id: I7e70ebe3c4879e7ab33a9c95a0c9e40408ff5ca4
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4680
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-15 14:56:01 +01:00
Alexandru Gagniuc 1b4cbafe1d cpu/allwinner/a10: Clarify positioning of boot stages
This fixes a number of potential issues, such as generating a build
failure if the bootblock is too large, and making sure romstage and
ramstage cannot overlap in memory.

Change-Id: I4ca9ad097b145445316bcd962e007731b08a7fda
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4687
Tested-by: build bot (Jenkins)
2014-01-14 14:15:25 +01:00
Alexandru Gagniuc 93b600ded7 cubieboard: Setup CPU clock in romstage and load ramstage
This completes the romstage for the cubieboard.

Change-Id: If3272d8a9e414f782892bc41b34b5e2dece5d7e1
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4686
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-14 14:15:12 +01:00
Alexandru Gagniuc 601b5b5302 cpu/allwinner/a10: Add helper to configure CPU clock
Change-Id: I5a3bb3220aeefdd6822a7dbecf210ff77095dad6
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4685
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-14 14:14:58 +01:00
Alexandru Gagniuc 594ef81326 lib: Add log2 ceiling function
Change-Id: Ifb41050e729a0ce314e4d4918e46f82bc7e16bed
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4684
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-14 14:14:46 +01:00
Alexandru Gagniuc 3dd0e72d3b lib/hexdump: Take const void * and size_t as arguments
Representing a memory location as an unsigned long is specific to
32-bit architectures. It also doesn't make sense to represent a length
assumed to be positive as a signed integer. With this change, it is no
longer necessary to cast a pointer to unsigned long when passing it to
hexdump.

Change-Id: I641777d940ceac6f37c363051f1e9c1b3ec3ed95
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4575
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-14 08:07:44 +01:00
Alexandru Gagniuc 8e053afa86 cubieboard: Configure system voltages from devicetree
Change-Id: I93bac9bf94f5bafcd3ff0c3d5763b31d3ee9959b
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4640
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-13 06:25:01 +01:00
Alexandru Gagniuc abe9b81e83 xpowers/axp209: Add helper to set voltages from devicetree config
Change-Id: I3ffe225b78f88c3c2d3a15292c43009e69413afb
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4638
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-13 06:24:54 +01:00
Alexandru Gagniuc af4bd599ca lib: Make log2() available in romstage on ARM, not just x86
On x86, log2() is defined as an inline function in arch/io.h. This is
a remnant of ROMCC, and forced us to not include clog2.c in romstage.
As a result, romstage on ARM has no log2().
Use the inline log2 only with ROMCC, but otherwise, use the one in
clog2.c.

Change-Id: Ifef2aa0a7b5a1db071a66f2eec0be421b8b2a56d
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4681
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-13 04:03:06 +01:00
Alexandru Gagniuc 910ce01757 cpu/allwinner/a10: Provide utility to make a bootable image
Up until now, we relied on mksunxiboot to prepend the header which
makes coreboot.rom bootable on Allwinner SoCs. If that tool was not
present, the build silently failed.

Integrate this tool into our util/ package, so that we do not have to
rely on mksunxiboot being in PATH.
Our version of mksunxiboot also eliminates some limitations of the
original tool, so we no longer have to use 'dd' to limit the file
size.

Change-Id: Id5a4b1e2a3cb00cd1d6c70e6cbc3cfd8587e8a24
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4656
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-13 04:03:00 +01:00
Alexandru Gagniuc d7b07af621 cpu/allwinner/a10: Clean up include order in Makefile.inc
Alphabetize the sources for each stage (bootblock, rom, ram), and
include twi.c in both romstage and ramstage.

Change-Id: I5526f5a66f6600560005731a3ee536eb858f4ff0
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4639
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-13 04:02:48 +01:00