The caller is already passing the address to the required LTE reset and
enable GPIO. During memcpy, the address to that pointer is used which
will lead to copying undefined data. Fix the pointer/address used in
memcpy.
BUG=None
BRANCH=dedede
TEST=Build Kracko, Drawcia and Metaknight mainboards which use this
function.
Change-Id: I79d6d9af03acd59ab5e1cd7df97bf451011dfeaa
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Found-by: Coverity CID 1458053, 1458054.
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56046
Reviewed-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This removes the need for type conversions all over the place.
Change-Id: I633a453aff17f1cbbe06b60e3efb67661733d06c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56029
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Do the usual type conversions
TESTED: Same image with BUILD_TIMELESS=1
Change-Id: Id44eeb7660d0b521a326a5b981c04c16cf0a6f84
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56019
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch sets the optimized FIVR configuration for adlrvp cutomized
based on the pnp measurements to achieve the better power savings in
sleep states.
* Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3,
S4, S5 states.
* Update the supported voltage states.
* Set the ICC max to 500mA for v1p05 and vnn.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I83e6910502d5cf9d4c26fa581272f59ac483ae19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This patch adds the supports to update the optimal FIVR
configurations for external voltage rails via devicetree.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: Icf6c74bda5a167abf63938ebed6affc6b31c76f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55702
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
brya0 is a reference and development platform, therefore it would be
helpful to have Crashlog enabled.
Change-Id: I936e73e808e0a05e8b7822cddbb5ee3fa7dee13e
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
The brya EC supports S0ix hang detection, but it was not enabled in
coreboot as well, masking that event out of S0ix, therefore add it in to
the EC S0ix wake mask.
TEST=After EC prints "Warning: Detected sleep hang! Waking host up!",
the host actually wakes up
Change-Id: I2c699114abcd9a045a41858c731e4b6fe99d3000
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Correct Bus and Device for THC0 and THC1
Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I41858ea156c8258ea0e7be9e2f67fb0e24144c80
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Allow to use the 2nd COM port of the AST2400 which can be also used via
IPMI/serial-over-lan.
Change-Id: I6f9c85b1f5428d3c3acf7a2f20296134c4611b1e
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
The -a flag was already implemented, it just wasn't exposed for the
add-payload command.
Setting the alignment of the payload will enable using the SPI DMA
controller to read the payload on AMD devices.
BUG=b:179699789
TEST=cbfstool foo.bin add-payload -a 64 ...
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I9f4aea5f0cbeaa8e761212041099b37f4718ac39
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
BUG=none
TEST=Boot with CONSOLE_LOGLEVEL_3 and no longer see the message printed.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0bdb92f547ceb8be624521211f4a3b94a91dae22
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This message is not an error, but just informational.
BUG=none
TEST=Boot with CONSOLE_LOGLEVEL_3 and no longer see it printed
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ifb64edbe029cafa82aec99aa50de47f51cd50dce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55971
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
We are currently reading the uCode for each CPU. This is unnecessary
since the uCode never changes.
BUG=b:177909625
TEST=Boot guybrush and see "microcode: being updated to patch id" for
each CPU. I no longer see CBFS access for each CPU. This drops device
initialization time by 32 ms.
Also boot Ezkinil and verify microcode was also updated.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I98b9d4ce8290a1f08063176809e903e671663208
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Start using the custom boot device.
BUG=b:179699789
TEST=Boot guybrush to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4ae7272677f563e8827ba154fe5177c8c01155c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This is a copy of mmap_boot.c and mem_rdev_ro_ops. I split it up so it
was easier to review.
The next patches will add support for the SPI DMA controller. This will
provide a minor speed up vs using mmap reads. It will also provide the
facilities to perform asynchronous SPI loading.
BUG=b:179699789
TEST=Boot guybrush to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Id26e2a69601d0f31e256d0010008904a447c8e21
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
In order to disable X86_TOP4G_BOOTMEDIA_MAP it requires the definition
to be overridden. This makes it a little less ergonomic to use. Instead
introduce the inverse option that can be selected. I chose to leave
X86_TOP4G_BOOTMEDIA_MAP since it keeps the Makefiles simple.
BUG=b:179699789
TEST=none
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I65bbc118bde88687a7d7749c87acf1cbdc56a269
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
On x86_64, the default heap size is too small when using 32 CPUs.
Change-Id: Ib4f770a7a54d975d213b2456cc7d1ed9151cb6f9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Introduce `USE_EXP_X86_64_SUPPORT` in `src/arch/x86/Kconfig` and guard
it with `HAVE_EXP_X86_64_SUPPORT`. Replace the per-CPU implementations
of the same functionality with the newly-added Kconfig options. Update
documentation and the config file for QEMU accordingly.
Change-Id: I550216fd2a8323342d6b605306b0b95ffd5dcd1c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55760
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Introduce the `ARCH_ALL_STAGES_X86` Kconfig symbol to automatically
select the per-stage arch options. Subsequent commits will leverage
this to allow choosing between 32-bit and 64-bit coreboot where all
stages are x86. AMD Picasso and AMD Cezanne are the only exceptions
to this rule: they disable `ARCH_ALL_STAGES_X86` and explicitly set
the per-stage arch options accordingly.
Change-Id: Ia2ddbae8c0dfb5301352d725032f6ebd370428c9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Add SPD support to eldrid for DDR4 memory part MT40A512M16TB-062E:R.
Eldrid should use DRAM_ID strap ID 0 (0000) on SKUs populated
with MT40A512M16TB-062E:R DDR4 memory parts.
BUG=b:192380070
TEST="FW_NAME=eldrid emerge-volteer coreboot" and verify it builds
successfully.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I4d07727c9c41bf494fbef373abce0ac1fc65c316
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55983
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There is no need to repeat "import" for each module in GoLang. Use
this keyword only once in each file for code cleanliness.
Change-Id: Ibb24fafd409b31b174946a39ca1f810d59b87e76
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55985
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In order to detect USB Type C device port as Super Speed, we need to set
corresponding bit in UPD UsbTcPortEn. This patch will use device path
to determine which port should be enabled.
BUG=b:184324979
Test=Boot board, USB Type C must be functional and operate at Super Speed.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: I7da63f21d51889a888699540f780cb26b480c26d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55361
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Since bootmem is not available in romstage, calls to bootmem APIs need
to be compile-time eliminated in order to avoid linker error:
undefined reference to `bootmem_region_targets_type
BUG=None
BRANCH=None
TEST=./util/abuild/abuild -p none -t GOOGLE_HEROBRINE -x -a -B
cherry-picked on top of CB:49392 and verified successful
compilation.
Change-Id: I8dfa2f2079a9a2859114c53c22bf7ef466ac2ad9
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55865
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently the flow for opregion init is as below:
1. Allocate memory for opregion first (cbmem_add(opregion))
2. Check if VBT size > 6 KiB (this requires extended VBT support)
3. In case of extended VBT requirement, we allocate another chunk
of memory which is equal to size of VBT (cbmem_add(extended_vbt))
4. Pass physical address pointer to OS via RVDA
We can optimize the above flow to allocate single chunk of memory by
checking VBT size in earlier step. The new optimized flow for opregion
init is as below:
1. Check if VBT size > 6 KiB (this requires extended VBT support)
2. In case of extended VBT requirement, total memory to be allocated
is calculated as sizeof(opregion) + sizeof (extended_vbt)
In case where VBT size is < 6 KiB, total memory requirement would
be equal to sizeof(opregion)
3. Based on above calculation, allocate single chunk of memory based on
total size.
This will also be helpful for the case of virtualization where guest
users don't have access to physical address and when it needs relative
address of VBT compared to absolute address.
In case of opregion 2.1 spec, we need to pass relative address of
VBT from opregion base in RVDA. This optimization will help in meeting
this requirement since relative address of extended VBT is easy to get.
This change will ensure that it meets opregion specification
requirement and will be compatible with future versions as well.
BUG=b:190019970
BRANCH=None
TEST=check the address of extended VBT region and address is coming
correctly.
Change-Id: Ic0e255df63145409096b0b9312c6c51c05f49931
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The dereferced parameter is never updated so passing a copy would work
too.
Change-Id: Ie36f64f55d4fc7034780116c28aaed65aa304d5e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55792
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
P-sensor is swap by the latest schematic. Thus, swap the IRQ for correct
P-sensor.
BUG=b:192331122,b:181555900
TEST=check P-sensor driver can be probed without error.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I3ccb31c1925e476e2ebb34b2439a491759472405
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The same pattern appears on all `xdci_can_enable()` call sites. Move the
logic inside the function and take the xDCI devfn as parameter.
Change-Id: I94c24c10c7fc7c5b4938cffca17bdfb853c7bd59
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This adds OEM variables feature under DPTF as per BWG doc #541817. Using
this, platform vendors can expose an array of OEM-specific values as OEM
variables to be used in determining DPTF policy. These are obtained via
the ODVP method, and then simply exposed under sysfs. In addition, these
gets updated when a notification is received or when the DPTF policy is
changed by userspace.
BRANCH=None
BUG=b:187253038
TEST=Built and tested on dedede board
Change-Id: Iaf3cf7b40e9a441b41d0c659d76895a58669c2fb
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This fixes building with libgfxinit in x86_64 mode, which can
generates unsupported R_X86_64_32S relocations without -mcmodel=large.
Change-Id: If5162fae475f3e70c856d9664a8cfc6a89d82283
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55549
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tidy up the code that programs the PAM (Programmable Attribute Map)
registers. Introduce the `D0F0_PAM` macro and use it to replace the
magic `0x59` and `0x5a` values in the code. Adjust the range of the
for-loop to work with the `D0F0_PAM` macro, and properly indent the
loop's body.
Change-Id: I9036425d726ffb69737ea6ed36c7a8f61d9d040a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Mainboard information can be found in the included documentation.
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: Idb696193e5a67c42adf45e54d455d2dff7681ca7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Create the cappy2 variant of the waddledee reference board by
copying the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:192035460
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_CAPPY2
Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com>
Change-Id: I772801152b9ca9c2c6afe76a353cb2b62d6210ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This changes updates mainboard properties by adding DFP number and
power_gpio for each DFP.
Reference CB:55348
BUG=b:191897776
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I63c912980530e5c9f341bdbab18c07685fd77abf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Add LTE modem to devicetree.
Configure GPIO control for LTE modem by fw_config.
Update LTE USB port configuration at run-time after probing FW_CONFIG.
By default the concerned USB port takes the Type-A port configuration.
BUG=b:186393848
TEST=Build image and check with command modem status
Change-Id: I20450ae37e5047dba67211316515994bd2a09600
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Update LTE USB port configuration at run-time after probing FW_CONFIG.
By default the concerned USB port takes the Type-A port configuration.
BUG=b:178092096
BRANCH=dedede
TEST=Build and boot to OS to check LTE by modem status
Change-Id: If12cc29ddda6d5c32c0bda840a3680e7bf932f89
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54671
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The `irq` variable has the same value as `pIntAtoD[line - 1]`.
Change-Id: Iabf760adbc3014b32cfe6f908dc04c38b71bd980
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
By enabling the flag alderlake platform will use hardware sha
instruction instead of software implementation for sha256.
This will speed up firmware verification especially on low-performance
device.
Change-Id: Ie8ab02360fdceafab257e9a301e6a89d3a22c3ae
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add Kconfig option for VBOOT_X86_SHA256_ACCELERATION, which will
use x86-sha extension for SHA256 instead of software implementation.
TEST=Able to call vb2ex_hwcrypto_digest_init() and perform SHA
using HW crypto engine.
Change-Id: Idc8be8711c69f4ebc489cd37cc3749c0b257c610
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Karthikeyan Ramasubramanian