Commit Graph

4647 Commits

Author SHA1 Message Date
Martin Roth 251e26683e util/lint: Add .gitignore files to list that don't need a license
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: I568a357b40e8bb69b2b26752d241f06adfbe029e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66503
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2022-08-11 17:53:48 +00:00
Martin Roth f67a1aa76a util/lint & LICENSES: Add PDDC as a "license" for coreboot
The Creative Commons Public Domain Dedication and Certification is not
a license in the common sense in that it's stating that the associated
file is already in the public domain (having no copyright), and is not
actually putting it in the public domain like the CC-C0 license does.

The use for this in coreboot is for unlicensable files - either blank
files or files with no creative content.  This allows these files to
have the SPDX identifier to identify them as having no known copyright
for open source license compliance.

If CC-PDM-1.0 is ever included in the list of SPDX licenses, that would
probably fit better, but because the public domain mark isn't actually
a license, and because "public domain" isn't well defined, CC-PDM was
rejected as a SPDX identifier.

For further information:
https://web.archive.org/web/20201018194411/https://github.com/spdx/license-list-XML/issues/988

Change-Id: Ibb300ecd066cde2a016195c2beca76a460c588e3
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66496
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-08-10 19:07:20 +00:00
Martin Roth afa3e5aa49 util/lint & LICENSES: Add GCC-exception-3.1 to license exceptions
The gcov files in the lib directory are licensed GPL 3.0 with the GCC
runtime library exception.

Add this as a valid license so that the files can get a correct SPDX
identifier.

Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: I1cf9c3125592741923c9b4481038055f24fe6ab1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-08-10 19:07:02 +00:00
Martin Roth 298b00776a utils: Add initial version of "remove_unused_code" script
This script creates a patch to remove all of the coreboot code that a
platform doesn't use.  This is useful for auditing the codebase for an
individual platform or releasing a platform's code.

Unlike the script that Sage used that did something similar, this keeps
the entire Kconfig tree (Though in a single file), all makefiles that
are required to build, and the standard build tools can still be used.
This will allow for much easier re-integration back into the coreboot
codebase if code is released after running this.

This is just the initial version and more features needed to be added to
make it fully functional.
- It should be able to build multiple configurations to retain the code
for all of those configurations.
- Flag to remove submodules files as well
- Additional variable flags to replace hardcoded values.
- The list of makefiles that need to be kept is pretty long, and could
be updated so that they aren't needed by the top level makefiles.
- Add flag to show changed files
- Show number of files before and after script is run

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Iec69db2ad1358846d649db627b6d60ac8c2204e4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-08-09 19:22:31 +00:00
Karthikeyan Ramasubramanian e5af14ace6 util/amdfwtool: Fix ISH_B directory offset
On boards which use both PSP recovery A/B layout as well as VBOOT A/B
layout, ISH_B directory entry is pointing directly to PSP Level2
directory. This is not correct and either ISH_B should be marked as not
present or it should point to the ISH_A directory itself which in turn
point to PSP L2 directory. Fix it by choosing the latter option.

BUG=None
TEST=Build and boot to OS in Skyrim with PSP verstage.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I0a7a56e98de3f85669ff8ec2fcd1687aa33576a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66445
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-09 16:44:47 +00:00
Subrata Banik 151dcf49a6 util/elogtool: Mark redundant boot mode event type as `deprecated`
This patch adds `_DEPRECATED_` tag to ChromeOS boot mode related event
logging types as below:

* ELOG_TYPE_CROS_RECOVERY_MODE <---- to record recovery boot reason
                                     while booting into recovery mode
* ELOG_TYPE_CROS_DEVELOPER_MODE <--- if the platform is booted into
                                     developer mode.
* ELOG_TYPE_CROS_DIAGNOSTICS <---- if the platform is booted into
                                     diagnostic mode.

Drop static structure `cros_deprecated_recovery_reasons` as it has been
replaced by vb2_get_recovery_reason_string() function.

ELOG_TYPE_FW_BOOT_INFO event type is now used to record all those
related fw boot info along with ChromeOS boot mode/reason etc.

BUG=b:215615970
TEST=Build and boot google/kano to ChromeOS.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I932952ce32337e2d54473667ce17582a90882da8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-08-06 14:06:33 +00:00
Jakub Czapiga aa41563483 util/cbfstool: Fix truncate command error handling and cbfs_image_from_buffer()
Check return value of cbfs_truncate_space() in cbfs_truncate().
Remove return from cbfs_image_from_buffer() to inform about invalid
image region when incorrect offset header was provided.
Also change header offset provided to mentioned function in
cbfs_expand_to_region() and cbfs_truncate_space() from zero
to HEADER_OFFSET_UNKNOWN, as they do not support images with cbfs master
header.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Ib009212692fb3594a826436df765860f54837154
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-08-03 23:24:49 +00:00
Subrata Banik 8b468400f1 util/cbfstool/elogtool: Support logging FW vboot info in elog
List of changes:
1. Add support for new elog event type to log vboot info (type 0xB7).
2. Add support string for fw_slot name, boot status and boot mode.
3. Print fw slot information like FW try count, FW current slot,
    previous FW slot, previous FW boot result and boot mode.

BUG=b:215615970
TEST=Able to build and boot google/kano to OS.
localhost # elogtool list
0 | 2022-07-01 11:10:27 | Log area cleared | 4088
1 | 2022-07-01 11:10:27 | Memory Cache Update | Normal | Success
2 | 2022-07-01 11:10:42 | System boot | 360
3 | 2022-07-01 11:10:42 | Power Fail
4 | 2022-07-01 11:10:42 | SUS Power Fail
5 | 2022-07-01 11:10:42 | ACPI Wake | S5
6 | 2022-07-01 11:10:42 | Wake Source | Power Button | 0
7 | 2022-07-01 11:10:42 | Chrome OS Developer Mode
8 | 2022-07-01 11:10:42 | Firmware vboot info |
                          boot_mode=Developer |
                          fw_tried=B | fw_try_count=0 |
                          fw_prev_tried=B | fw_prev_result=Unknown
9 | 2022-07-01 11:11:42 | System boot | 361
10 | 2022-07-01 11:11:42 | System Reset
11 | 2022-07-01 11:11:42 | Firmware vboot info |
			  boot_mode=Developer |
			  fw_tried=B | fw_try_count=0 |
			  fw_prev_tried=B | fw_prev_result=Success

localhost # crossystem recovery_request=1
localhost # elogtool list
41 | 2022-07-13 12:13:48 | Firmware vboot info |
			  boot_mode=Manual recovery boot |
		          recovery_reason: 0x1/0 (Recovery requested
			  from legacy utility) | fw_tried=A |
			  fw_try_count=0 | fw_prev_tried=A |
			  fw_prev_result=Unknown

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I48b5d54723683cef51e416fc6f58da000507fbcc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65562
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-02 07:06:52 +00:00
Karthikeyan Ramasubramanian 0b4f49c792 util/spd_tools/spd_gen/lp5: Remove maxSpeed for Sabrina
Firmware component that does memory training already limits the memory
controller to train at 5500 Mbps for all memory parts in Sabrina. Hence
removing this interim SPD change to limit the speed.

BUG=b:238074863
TEST=Build and boot to OS in Skyrim.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I2bc82c7407a97aac282708c3e0bd56ae99a8fc31
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66290
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-01 20:30:39 +00:00
Karthikeyan Ramasubramanian 51f914d4a4 util/amdfwtool: Support PSP whitelist file on recovery A/B layout
This is required to enable PSP verstage on SoCs with recovery A/B
layout.

BUG=b:217414563
TEST=Ensure that the concerned type 0x3a PSP entry is present in PSP L2
directory. Build and boot to OS in Skyrim with both PSP and x86
verstage.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I5fae2b5dbcc95a99af3df9f59bb8516280ec1281
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-08-01 12:34:46 +00:00
Elyes Haouas ae157d38e3 crossgcc: Upgrade LLVM from 13.0.1 to 14.0.6
Test build for QEMU x86 i440fx/piix4.

Change-Id: I97d059947f7049b2491a98985795a4655891c3b3
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-07-30 18:27:30 +00:00
Felix Singer dca8583f17 util/liveiso/common: Install devmem2 and pcimem
devmem2 and pcimem are useful tools which allow working (reading and
writing) with memory mapped IO.

Change-Id: Ifda547b44af3c8e11cd4171a1dfbce3713455303
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66171
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-28 18:28:24 +00:00
Karthikeyan Ramasubramanian 234e37099a util/amdfwtool: Update the location of PSP verstage and signing key
On SoCs which use A/B recovery layout, PSP verstage and signing keys are
expected to be present only in PSP L2 directory. Update amdfwtool to
include the PSP verstage and signing key only in PSP L2 directory.

BUG=b:239519603, b:238938623
TEST=Build and boot to OS in Skyrim with PSP verstage.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ieeb415be800b7ccf10d6983eb0b567e0a5eaa955
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-07-26 20:36:04 +00:00
Patrick Georgi a284a36535 util/kconfig: Add README.md documenting the uprev procedure
Change-Id: I2e74f1c5cb1657e11d4f7ea101549329274102db
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-07-22 19:27:32 +00:00
Karthikeyan Ramasubramanian d5ea355c73 util/spd_tools: Limit memory speed to 5500 Mbps for Sabrina
In Sabrina platform, memory speed is limited to 5500 Mbps. Update the
SPD generation tool to limit to that speed.

BUG=b:238074863
TEST=Build and boot to OS in Skyrim.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ie3507898167012e0d812c9b1aacba72e9055fcd8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-07-19 15:11:53 +00:00
Elyes Haouas 50eef6566b lint/checkpatch: Add check for used comma where semicolon could be
This reduce the difference with linux v5.19-rc7.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I6d3a49378008bad61b2a18bd8cb28be952a18006
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-07-19 01:48:35 +00:00
Elyes Haouas f9a3554a4a lint/checkpatch: Add a check for use of self-assignments
This reduce the difference with linux v5.19-rc7.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: If47a7826ee67a2be25a4caa2a447484e5f11411b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-07-19 01:48:24 +00:00
Elyes Haouas e83e090b05 lint/checkpatch: Add a check for existence of a commit log
This reduce the difference with linux v5.19-rc7.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I4e3b98140d900c5717f4badde71c7be88fd1e23a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-07-19 01:48:13 +00:00
Elyes Haouas 6e84c2ca70 lint/checkpatch: Update 'Check patch "separator" and "signoff"'
This reduce the difference with linux v5.19-rc7.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Id3d7375216af5bf75ed7ce61fa8ea2dfebe8ac77
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-07-19 01:47:59 +00:00
Elyes Haouas cb346842ad lint/checkpatch: Update 'check for unwanted Gerrit info'
This reduce the difference with linux v5.19-rc7.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I856bfa0f0d39fda549671b1029cccdc39f831bab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-07-19 01:47:49 +00:00
Elyes Haouas e235a0de18 lint/checkpatch: Update 'uncoalesced string fragments'
This reduce the difference with linux v5.19-rc7.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I21b2a0d87cbf610fc48e273ed78ab779ad4a6932
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-07-19 01:47:34 +00:00
Elyes Haouas 71bfcf528d lint/checkpatch: Update 'concatenated string without spaces between elements'
This reduce the difference with linux v5.19-rc7.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I04e58aca4a30e82f3da0cda08403d0daf3b5fb10
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-07-19 01:47:17 +00:00
Elyes Haouas a59a87ca17 lint/checkpatch: Update 'check indentation of a line with a break'
This reduce the difference with linux v5.19-rc7.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I79170a45cd8184ebc816b4f16656a3cfdc257f60
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-07-19 01:46:40 +00:00
Elyes Haouas d92fcf448f lint/checkpatch: Update 'check for logical continuations'
This reduce the difference with linux v5.19-rc7.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I222e3378ded4cd73d0141cd1e38ac3282d311cc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65827
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-07-19 01:46:22 +00:00
Elyes Haouas 86e4a3ae05 lint/checkpatch: Update 'check for adding lines without a newline'
This reduce the difference with linux v5.19-rc7.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I1bd68e9a6609a3dfa7dc856f24e4b616714d9990
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-07-19 01:46:09 +00:00
Elyes Haouas c5ede53ba8 lint/checkpatch: Update 'check for assignments on the start of a line'
This reduce the difference with linux v5.19-rc7.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ia7d4b0176bad849e79f037f74c3d99ce9eb061c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-07-19 01:45:55 +00:00
Yu-Ping Wu fcfc572947 util/xcompile/xcompile: Define GCOV_${TARCH}
When payloads analyze the coverage using gcov (or lcov), the gcov
version must match the CC version. Otherwise gcov would fail to parse
the .gcno files.

Therefore, define GCOV_${TARCH} in xcompile, so that payloads don't need
to do tedious string manipulations to find the right gcov path.

Change-Id: If2fc329810c463a3d2c56deaf4e4a3fc3c0a3ed9
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
2022-07-15 05:59:38 +00:00
Bill XIE ac136250b2 commonlib: Substitude macro "__unused" in compiler.h
Since there are many identifiers whose name contain "__unused" in
headers of musl libc, introducing a macro which expands "__unused" to
the source of a util may have disastrous effect during its compiling
under a musl-based platform.

However, it is hard to detect musl at build time as musl is notorious
for having explicitly been refusing to add a macro like "__MUSL__" to
announce its own presence.

Using __always_unused and __maybe_unused for everything may be a good
idea. This is how it works in the Linux kernel, so that would at least
make us match some other standard rather than doing our own thing
(especially since the other compiler.h shorthand macros are also
inspired by Linux).

Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I547ae3371d7568f5aed732ceefe0130a339716a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-07-14 23:08:09 +00:00
Jack Rosenthal f77fa2f7a9 util/spd_tools: Add support for 7500 MT/s lp5 modules
spd_tools does not support LP5x modules yet, and the easiest way to do
this is to add support for 7500 MT/s in lp5.go (reference the comments
on CB:65063).

BUG=b:238674174
BRANCH=firmware-brya-14505.B
TEST=With follow-on CL, run:
     util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5

Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I1558d69bc6f28c02c20aa9cd87d4543c1cf52afd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
2022-07-14 21:27:01 +00:00
Subrata Banik 123bcb702a util/spd_tools: Add Intel Meteor Lake (MTL) platform
This patch add support for MTL platform to the `spd_tools`.
This would be useful to create dynamic SPD for rex variants.

BUG=b:224325352
TEST=Able to generate SPD for LP5 DRAM part.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I1db6e3a63d2842c12ef0f256ba1d32b9258670f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65473
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-07-14 12:50:10 +00:00
Petr Cvek 61f3f33311 Remove executable flag from source codes and text files
Markdown, definition file and sconfig source codes don't need to be
executables. This patch fixes that.

Signed-off-by: Petr Cvek <petrcvekcz@gmail.com>
Change-Id: Ic97d684318c689259f7895e3dfbd552434c3882e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-07-14 12:46:07 +00:00
Tim Crawford 5c2b5fcf2f util: Allow installing to a build root
Modify util Makefiles to allow installing to a build root specified by
DESTDIR. Allows using the `install` target for packaging.

Change-Id: I3a31ea0fde9922731e1621dcc8f94b2c1326c93c
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60540
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-07-12 22:11:35 +00:00
Paul Menzel 1ff6125af7 util/release/build-release: Use `git log … -1` over `|head -1`
Avoid piping to `head` to print the top line, and do it in `git log`
directly.

Change-Id: Id9b99b06c5bdd9c381bd039fc1914a9a2f332aa6
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64941
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-07-06 19:21:35 +00:00
Jon Murphy c4e90454f4 treewide: Unify Google branding
Branding changes to unify and update Chrome OS to ChromeOS (removing the
space).

This CL also includes changing Chromium OS to ChromiumOS as well.

BUG=None
TEST=N/A

Change-Id: I39af9f1069b62747dbfeebdd62d85fabfa655dcd
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65479
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-07-04 14:02:26 +00:00
Fred Reitberger f36b0138c4 util/amdfwtool: Initalize all variables before use
Not all of the fields of the amd_cb_config structure were properly
initialized. Rather than initialize each field individually, initialize
the entire structure to 0.

TEST: Boot chausie

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ia343f01bce3956d66d01ce485b43963193c9df31
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-06-30 19:08:14 +00:00
Elyes Haouas f6abb9ef8d crossgcc: Upgrade CMake from 3.23.0 to 3.23.2
Change-Id: I3613522fa2a958d2a42674f17aa794bdda4ca74a
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63123
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-27 22:21:50 +00:00
Evgeny Zinoviev c3566b67f6 nvramtool: Fix building on Linux systems with musl libc
Current implementation only supports glibc (by looking for __GLIBC__)
and fails to build on systems with alternative libc implementations,
such as musl; sys/io.h is never included, there are no outb/inb
functions which results in undefined references at linking stage.

Using __linux__ instead of __GLIBC__ to test whether the system is Linux
seems to be a more proper way to detect Linux and it also fixes
nvramtool compilation on musl systems.

Tested on Gentoo Linux with musl 1.2.2 (builds and works fine) and Void
Linux with glibc (still builds and works fine).

Change-Id: Idcdc3a033b40f16a6053209813f1e06209ee459a
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48757
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-23 12:19:52 +00:00
Arthur Heymans 0424a2c59f util/ifdtool: Fix printing or setting PCH straps
When printing or setting the PCH straps use the PSL directly instead
of multiplying it by 4.

Change-Id: Ia91697fdf0c6d80502e8611b259c444f39c6cd57
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2022-06-23 12:17:54 +00:00
Martin Roth 93333cb34e util/lint: Add coreboot specific dictionary file
This is a wordlist that I've compiled to use in spellcheckers to ignore
all of the coreboot specific terms.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I718519000eaf31786380474eb71b99ca442e3bed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-06-22 21:40:19 +00:00
Arashk Mahshidfar e607ddc5c9 util/inteltool: Add an additional Device ID for Intel HD 4400 GPU
Add 0x0A16 as a Device ID for Intel HD 4400

Change-Id: I0129376c0ce005c1bfabaa9dbd8d8dfc6c92e5d3
Signed-off-by: Arashk Mahshidfar <arashkmahshidfar@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2022-06-22 00:51:30 +00:00
Angel Pons bb58c1e438 util/cbfstool: Set `USE_FLASHROM=0` to build vboot
cbfstool does not need to build vboot with flashrom support.

TEST=./util/abuild/abuild -a --timeless -y -c $(nproc) -Z -t hp/280_g2
     no longer fails due to missing libflashrom.h header.

Change-Id: I57edcb1b67baa4c458874b11e9ca0238b4419c46
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-06-19 18:46:04 +00:00
Edward O'Callaghan 01dbba5e3d util/cbfstool/common.c: Deduplicate buffer_create() logic
BUG=b:207808292,b:231152447
TEST=builds with vboot_ref uprev.

Change-Id: Id7d9b6f5254b08720eebb37151e12ee68ed7f8d7
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65145
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-16 20:38:53 +00:00
Edward O'Callaghan 774dcffc36 util/cbfstool: Decouple elogtool from vboot_ref flashrom code
Currently elogtool sub-proccesses flashrom as calling libflashrom
requires a missing function from the previous flashrom release.
Pending a new release of flashrom we must continue to use subprocess.

However the current subprocess wrapper implementation lives in
vboot_reference which is a git sub-module of coreboot. This causes
all sorts of grief keeping a subprocess ABI stable from vboot_reference
when the rest of vboot_reference builds of HEAD of the flashrom tree
(i.e., using unreleased libflashrom functions). In order to not keep
finding ourseleves in a bind between the two separately moving trees
with different build environments, decouple elogtool with its own
mini copy of flashrom subprocess wrapping logic.

Squash in,
 util/cbfstool/elogtool.c: Convert args into struct in flashrom helper

  vboot signatures for flashrom r/w helpers changed in the upstream
  commit bd2971326ee94fc5. Reflect the change here to allow vboot ref
  and coreboot to realign.

BUG=b:207808292,b:231152447
TEST=builds with vboot_ref uprev.

Change-Id: I04925e4d9a44b52e4a6fb6f9cec332cab2c7c725
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-06-16 20:38:41 +00:00
Shou-Chieh Hsu 446bacd2f4 util/mb/google: add support for nissa
Add the file template for creating a new variant of Nissa.

BUG=b:229550821

Signed-off-by: Shou-Chieh Hsu <shouchieh@google.com>
Change-Id: I04f75ff91f9851b82641f703ba950b04c22e2e72
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64045
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-06-14 00:53:14 +00:00
Felix Singer 3e94068508 util/liveiso: Update to NixOS 22.05
Update configs for NixOS 22.05.

pulseaudio-modules-bt has been abandoned, and is superseded by
pulseaudio's native Bluetooth functionality. Thus, remove it.

Change-Id: Ic3b1dbc3c2ab092b576ba2151c93c74d4f298efc
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64969
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-06-13 20:12:33 +00:00
Nico Huber f9b5665d28 crossgcc/gnat.patch: Add additional gnatlib object files
Newer host versions of gnatbind miss these when building the cross
gnat1 and gnatbind.

Tested with the following host compilers with and without bootstrapping
that the resulting coreboot images of three boards stay the same:
* GCC 4.9.2 (Debian)
* GCC 6.3 (Debian)
* GCC 7.4 (Debian)
* GCC 8.3 (Debian)
* GCC 9.4 (Debian)
* GCC 10.2 (Debian)
* GCC 12.1 (ArchLinux)

Change-Id: I09c6b3cc7b15f1c505acd3ec2c1959b101d6dfb7
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65000
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-10 14:09:32 +00:00
Nico Huber 0b2a632005 crossgcc/gnat.patch: Never treat warnings as errors
We used to disable individual warnings that are expected when building
our GCC version with a newer one. Not all warnings can be disabled
indvidually, though, and it's much easier to simply allow warnings.
As a plus, we get the warnings in the log (in case anybody would ever
look into it).

Partially fixes building with host GCC 12.1.

Change-Id: I8fafec4fc49db73b6dba311c775eea2cc92a9b48
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-10 14:08:57 +00:00
Martin Roth 124c418ccf util/util_readme: update to give additional information
Add a note to the top of the util.md document saying not to edit it.

The Documentation/util.md file had been updated to contain additional
information at the bottom.  This copies that information into the file
after it's been created.

Change-Id: I4b08439420ceb706df62e3949406585ea34c1514
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-06-07 15:49:56 +00:00
Martin Roth 56846091f1 util, Documentation: Run util_readme.sh to regen util.md
Change-Id: Ie14204d0637bb5081e2fae4a9a0e2590bf7abeeb
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-06-07 15:49:27 +00:00
Julius Werner 423cd06fa6 cbfstool: Expand CBFS verification validity check
This patch adds a new line to `cbfstool print -v` output that records
the overall CBFS verification health of the image. While this info was
already visible from individual fields before, it's nice to have a
one-stop location to see "this is a good image" without having to
carefully parse a lot of output manually.

Also add a few lines to the Makefile that check whether this field is
valid for the final image (it always should be, but hopefully this check
will allow us to catch regressions like the one fixed by CB:64547 sooner
in the future).

BUG=b:233263447

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I1b74b01a55b22294556007aaee835d0fdb9e1c63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-06-07 12:57:25 +00:00
Michał Żygowski de91780c30 inteltool/gpio_names/tigerlake.h: Fix HVMOS pad count
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I344fd2db9d53ad5e82240aaa2b766ac0d8a2045d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64464
Reviewed-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-06-03 20:06:01 +00:00
Patrick Georgi 7310789085 util/scripts/cross-repo-cherrypick: Modify output format
As far as I know the Chromium OS team is the only user of this script,
so align its output with that of other tools used there:

- Replace "Original-Commit-Id" with "GitOrigin-RevId"
- Reuse Change-Id instead of moving it to the Original- prefix, which
  leads to the creation of a new Change ID.

Change-Id: I8c39c512901c83a64f00aa48a539e6621f827242
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-06-03 18:44:51 +00:00
Martin Roth 8da4bfe5b5 util/release/build-release: Use short git hash for .coreboot-version
Builds were suddenly failing when the release was done, because the
coreboot version was overflowing a 64 character limit.  We don't need
or use the full hash in other places, so limit the hash to just what's
needed to identify the commit.

Change-Id: I57c535ca251792cae2c9a9c951e6b44bb61e4e78
Signed-off-by: Martin Roth <martin@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-06-03 03:10:05 +00:00
Julius Werner af20fd748b cbfs: Add CBFS_TYPE_INTEL_FIT and exclude it from CBFS verification
The Intel Firmware Interface Table (FIT) is a bit of an annoying outlier
among CBFS files because it gets manipulated by a separate utility
(ifittool) after cbfstool has already added it to the image. This will
break file hashes created for CBFS verification.

This is not actually a problem when booting, since coreboot never
actually loads the FIT from CBFS -- instead, it's only in the image for
use by platform-specific mechanisms that run before coreboot's
bootblock. But having an invalid file hash in the CBFS image is
confusing when you want to verify that the image is correctly built for
verification.

This patch adds a new CBFS file type "intel_fit" which is only used for
the intel_fit (and intel_fit_ts, if applicable) file containing the FIT.
cbfstool will avoid generating and verifying file hashes for this type,
like it already does for the "bootblock" and "cbfs header" types. (Note
that this means that any attempt to use the CBFS API to actually access
this file from coreboot will result in a verification error when CBFS
verification is enabled.)

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I1c1bb6dab0c9ccc6e78529758a42ad3194cd130c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-01 19:45:22 +00:00
Julius Werner 0057262b38 cbfs: Rename TYPE_FIT to TYPE_FIT_PAYLOAD
There are too many "FIT" in firmware land. In order to reduce possible
confusion of CBFS_TYPE_FIT with the Intel Firmware Interface Table, this
patch renames it to CBFS_TYPE_FIT_PAYLOAD (including the cbfstool
argument, so calling scripts will now need to replace `-t fit` with `-t
fit_payload`).

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I826cefce54ade06c6612c8a7bb53e02092e7b11a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-06-01 19:45:08 +00:00
Martin Roth b3f91b7941 util/docker: Update dockerfiles
- Remove deprecated "MAINTAINER" lines
- Add Sphinx tools to coreboot-jenkins-node to check documentation.
- Add mdl to check markdown
- Alphabetize packages in docs Dockerfile
- Add jinja2 version 3.0.3 to the docs Dockerfile - The latest version
breaks with the error:
"exception: cannot import name 'contextfunction' from 'jinja2'"

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ia1de62621a6aef4ecd055a1a3afbebad34448002
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-05-31 13:41:56 +00:00
Martin Roth 74129e5141 util: Update description files
- Spelling fix
- Add languages
- Update formatting
- Move notes that shouldn't be in the description file to a README

Change-Id: I4af37327d5834f8546a3f967585658fb5686f17a
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-05-30 13:05:21 +00:00
Martin Roth e44a3d2842 util: Fix a few spelling mistakes
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ib6f0232292c9e289ee1e87998493ea70beea8e78
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-05-30 04:25:07 +00:00
Martin Roth 81e0d689c0 Documentation: Move intelp2m from description.md to Documention
The description.md file for the intelp2m utility wasn't the description
that was needed - just a subject, and what language it was written in.
It was instead a set of more full documentation, so move it into the
Documentation directory and create a new description file.

Change-Id: Ia180ae41f91f8b8eb408351a9e44e899edc031d3
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-05-30 04:19:39 +00:00
Elyes Haouas 709fdb1995 util/lint/checkpatch: Add alloc functions to alloc with multiplies check
This reduce difference with linux v5.18.

Change-Id: Id9412f7b6c0b9f76b39a094142aaded5c2aa1059
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-29 14:55:38 +00:00
Elyes Haouas 069dfe33a3 util/lint/checkpatch: Update 'Check for compiler attributes'
This reduce difference with linux v5.18.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I817630321587dec515cd94aa7b73a17819526190
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-29 14:55:21 +00:00
Elyes Haouas a7b0d38964 util/lint/checkpatch.pl: Use 'allocFunctions'
This reduce difference with linux v5.18.

Change-Id: I1fc71b9cb6a4e4f8b27fbe6d45f4fa4e2c236157
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-29 14:55:02 +00:00
Michał Kopeć 2d8edebc97 util/inteltool: Add support for Alder Lake chips detection and GPIOs
Add PCI IDs for Alder Lake H devices and their GPIO tables.

PCI IDs as per Intel PCH-H EDS Vol1 (doc #619362).

TEST=dump GPIOs on i5-12600K with Z690 chipset

Change-Id: I0001395517e1e7977b0f808d5d74cf85c52298d6
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2022-05-28 14:36:50 +00:00
Arthur Heymans c2eb9e6e81 abuild: Build with clang only when supported
This changes the behavior of '-L/--clang' to only buildtest when a
target has ARCH_SUPPORTS_CLANG set.

Change-Id: I362fcd0f795d27f13dde793a79774f08c497bd38
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-28 05:23:21 +00:00
Martin Roth 97e7eea976 util/lint/checkpatch: Warn on period at the end of commit subject
This gives a warning when there's a period at the end of the commit
subject line.

Change-Id: If95bef3ba01e0ac13ce18045928081040abef4fd
Signed-off-by: Martin Roth <martin@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63032
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-05-28 01:26:03 +00:00
Martin Roth 341a53d1c5 util/lint: Subtract the patch format string from subject length
Checkpatch was looking for a 65 character length, but format-patch adds
the text "Subject: [PATCH] " before the actual subject.  Checkpatch
needs to account for that when looking at the line length.

Lines 2863 & 2864 have their indentation fixed as well.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I2f2ee6e0f1b14ae6393ed7e64ba1266aa9debc7d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-05-28 01:25:48 +00:00
Martin Roth 9e33723d9b util/lint: Add commit message parsing to checkpatch_json script
The commit message wasn't being parsed because there's no filename
associated with it in the patch output.  This change adds the "filename"
for the commit message in Gerrit for any errors that have a line number
but no filename.

calculations is intentionally misspelled as cacluations as a test.

Change-Id: Ie7a2ef06419c7090c8e44b3b734b1edf966597cc
Signed-off-by: Martin Roth <martin@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-05-28 01:25:37 +00:00
Michał Kopeć d3b550d47c util/intelp2m: Add support for Alder Lake macro generation
Add support for Alder Lake as a separate parsing profile, copying the
existing 'Cannon' profile and adjusting for differences in reset mapping
and GPIO macro generation.

TEST=Generate GPIO macros for MSI PRO Z690-A

Change-Id: I5871394bcb0636c2c803607ffb129441aa934417
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2022-05-25 23:25:25 +00:00
Elyes Haouas 26e0b94614 util/lint/checkpatch.pl: Reduce difference with linux v5.18
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Id5eb4823399088746a34721a9855bbaf5f97b7b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-24 12:57:48 +00:00
Maximilian Brune 94223c4165 Allow trailing whitespaces in .md files
Two trailing whitesspaces have an actual meaning in Markdown files (a new line).

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ibdb92ee857ee4ad32b6afb84ace427b27b41bb7c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64032
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-16 19:58:31 +00:00
Robert Zieba 4098ecf5bd util/testing: Remove amdfwread from makefile
amdfwread was added to the testing makefile but ended up not becoming a
separate tool. This commit removes it from the makefile so that `make
distclean` works again.

Fixes: 29bc79fddb ("util/amdfwtool: Add
amdfwread utility")

TEST=Ran `make distclean`

Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: I2c8b920bc69d6c20558a28515c52a1e9cecebe27
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64348
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-16 15:56:50 +00:00
Sean Rhodes 645dde7794 util/inteltool: Add support for Gemini Lake
Tested on:
* StarLite Mk III (N5000)
* StarLite Mk IV (N5030)

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I0ef7619c04db66ea0c6e179bdf0a58ed1ab61a48
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-16 07:04:22 +00:00
Martin Roth af06e9adea util/lint/lint-stable-019: Update grep '\s' to [[:blank:]]
For some reason, the '\s' syntax is causing an error for me under
freebsd.  It's entirely possible that I'm doing something wrong, but
this change should be fine regardless.

Freebsd's grep, GNU grep, and git grep all handle posix regex classes,
so this change should be transparent.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I489ec13b4ea2e9c17692888e42b8741763b1a2c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-05-16 05:18:09 +00:00
Elyes Haouas 14c49e3646 util/lint/checkpatch.pl: Fix "uninitialized value" error message
Change-Id: I74807f240779060158c6769f63a6e9438a6e5fbe
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-16 02:28:44 +00:00
Elyes Haouas 0014bce46b util/lint/checkpatch.pl: Fix "Invalid color mode" error message
Remove duplicated code:
"if ($color =~ /^[01]$/) {
	$color = !$color;
} elsif ($color =~ /^always$/i) {
	$color = 1;
} elsif ($color =~ /^never$/i) {
	$color = 0;
} elsif ($color =~ /^auto$/i) {
	$color = (-t STDOUT);
} else {
	die "$P: Invalid color mode: $color\n";
}"

Change-Id: I5713c364edea806e58df26c3a37b4bba7603ed0a
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-16 02:28:02 +00:00
Robert Zieba 29bc79fddb util/amdfwtool: Add amdfwread utility
Amdfwtool creates AMD firmware images however there is currently no way
to get information from an existing image. This commit adds amdfwread to
support that functionality. At the moment only reading PSP soft fuse
flags is supported. Example usage: `amdfwread --soft-fuse bios.bin`,
example output: `Soft-fuse:0x400000030000041`.

BUG=b:202397678
TEST=Ran amdfwread and verified that it correctly reads the soft fuse
bits, verified that built AMD FW still boots on DUT

Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: I15fa07c9cad8e4640e9c40e5539b0dab44424850
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-05-13 15:51:37 +00:00
Arthur Heymans a0595759f6 xcompile,clang: increase the number of bracket-depth for CPP
Clang has a limit for the number of nested brackets in CPP.
For soc/intel/common/block/include/intelblocks this is a problem as it
largely exceeds the default limit of 256.

Change-Id: I93038f918e07f735394fc495a8ed7371cc5b1569
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62175
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-13 11:03:16 +00:00
Karthikeyan Ramasubramanian 0ab04d2851 util/amdfwtool: Add IKEK key for Trusted Application
This binary file is required for use by Trusted Applications that
execute in PSP.

BUG=b:229947314
TEST=Build and boot to OS in Skyrim.

Change-Id: I2d05792cfd98fa9c38f5deef1ac3282625983eeb
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-05-05 14:48:31 +00:00
Yu-Ping Wu f1a8dde147 cbfstool: MediaTek: Hash bootblock.bin for CBFS_VERIFICATION
MediaTek's bootROM expects a SHA256 of the bootblock data at the end of
bootblock.bin (see util/mtkheader/gen-bl-img.py). To support CBFS
verification (CONFIG_CBFS_VERIFICATION) on MediaTek platforms, we need
to re-generate the hash whenever a file is added to or removed from
CBFS.

BUG=b:229670703
TEST=sudo emerge coreboot-utils
TEST=emerge-corsola coreboot chromeos-bootimage
TEST=Kingler booted with CONFIG_CBFS_VERIFICATION=y

Change-Id: Iaf5900df605899af699b25266e87b5d557c4e830
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63925
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-05 14:18:38 +00:00
Martin Roth 3201e1e68c util/scripts: Add options to update_submodules
This extends and adds various options to the update_submodules script.

Extensions:
- Add help text
- Add all options, but specifically allow a single repo to be specified,
along with a minimum number of changes instead of being fixed at 10.
- Make it a more formal script with main() and functions
- Show changes in commit message, unless there are > 65 commits.

Options:
-c | --changes <#>     Specify the minimum number of changes to update a repo
-h | --help            Print usage and exit
-R | --repo <dir>      Specify a single repo directory to update
-s | --skipsync        Assume that repos are already synced
-V | --version         Print the version and exit

This does not fix style issues in the original, which will be fixed in
a follow-on commit.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I222103babff7d5f4f8eb02869c598a4e06748a17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-05-04 13:12:23 +00:00
Manoj Gupta dfb8d80c1a utils/cbfstool: Disable Wstrict-prototypes warning
As recommended on crrev.com/c/3612466 lz4 code is not supposed
to be modified. Since both gcc and clang complain about
functions without explicit void in argument with Wstrict-prototypes,
just disable it instead instead of enabling.

BUG=b:230345382
TEST=llvm tot test
BRANCH=none

Signed-off-by: Manoj Gupta <manojgupta@google.com>
Change-Id: I9f3ae01821447f43b4082598dd618d9f8325dca2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63936
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-02 21:02:57 +00:00
Nick Vaccaro 946e29258c util/cbmem: fix an unused parameter issue in timestamp_get
Fix an unused parameter error when building on devices where __i386__
and __x86_64__ are not defined.

BUG=none
TEST=none

Change-Id: I6c04c8e7b931565c87d358aac1025ebcb7617b13
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63880
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-27 00:32:29 +00:00
Zheng Bao 993b43f2be amdfwtool: Use command line option use-combo to decide if use combo
The macro PSP_COMBO is removed and instead use the flag use_combo. As
long as this flag is false, the amdfwtool behaves the same way as the
macro does.

Change-Id: Ief0d78ae1e94b8183d6cf3195935ff9774fee426
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-25 14:48:16 +00:00
Zheng Bao 96a3371a72 amdfwtool: Change the name of macros for 'BHD'
Use BHD instead of BDT as the name of cookie macro. Use L2 to make it
clear it is for level 2. The 'BHD2' is misleading, which is going to
be used for combo entry. The definition in psp_verstage is also changed.

Change-Id: Ia10ac5e873dab6db7d66e63773a7c63f504950b2
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-25 14:46:12 +00:00
Arthur Heymans 597b9e9d71 cpu/x86/64bit: Generate static page tables from an assembly file
This removes the need for a tool to generate simple identity pages.
Future patches will link this page table directly into the stages on
some platforms so having an assembly file makes a lot of sense.

This also optimizes the size of the page of each 4K page by placing
the PDPE_table below the PDE.

Change-Id: Ia1e31b701a2584268c85d327bf139953213899e3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-04-25 14:00:41 +00:00
Elyes Haouas 43529c8b20 util/lint/checkpatch.pl: Update lines related to CONST_STRUCT
Update to v5.18-2 version.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I0fe2ec6a74a4b8c70452fbf05d534a37e1ea2c26
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <martinroth@google.com>
2022-04-24 21:19:40 +00:00
Elyes Haouas f0e150c35a util/lint/checkpatch.pl: Add strlcpy check
Update to v5.18-2

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ic4eaa3f26bcd60ea509a52d5715c7ce1f43b6d3d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <martinroth@google.com>
2022-04-24 21:18:55 +00:00
Elyes Haouas 8f59960fb2 util/lint/checkpatch.pl: Update C99_COMMENT_TOLERANCE lines
Update to v5.18-2 version.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: If230fa5cd01ab3ce91d8c910667c3d609cf978b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <martinroth@google.com>
2022-04-24 21:18:11 +00:00
Elyes Haouas 00d8ffdada util/lint/checkpatch.pl: Update TYPECAST_INT_CONSTANT lines
Update to v5.18-2 version.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I8ed89e53f647b1b071abff33a434fb3b8dbb1de1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <martinroth@google.com>
2022-04-24 21:17:34 +00:00
Elyes Haouas 84083a27aa util/lint/checkpatch.pl: Update the check of repeated words
Update to v5.18-2 version.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I7f5e597bb76e1b9feeb2d6ea290626f45e9fe6c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <martinroth@google.com>
2022-04-24 21:17:00 +00:00
Elyes Haouas f62a98939d lint/checkpatch.pl: Update to v5.18-2 lines related to "CONFIG_"
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I8589d053871ad9ac64ae2f8fc380710be8e4556b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <martinroth@google.com>
2022-04-24 21:16:14 +00:00
Elyes Haouas 0b1a03cd18 util/lint/checkpatch.pl: Update lines related to max_line_length
Upadate to v5.18-2 version.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ib9927bfa98e20d4b621bf7abecec234b4754ee9c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <martinroth@google.com>
2022-04-24 21:16:04 +00:00
Elyes Haouas 41d43f5eeb util/lint/checkpatch.pl: Update lines related to tabsize
Update to v5.18-2 version.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I6651a3f8e79beca2e1235fe8de3217875f81ba2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <martinroth@google.com>
2022-04-24 21:15:33 +00:00
Elyes Haouas 46b07e53f5 util/lint/checkpatch.pl: Update to v5.18-2 lines related to verbosity
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I66f38cb01e58ee241bf58c4db83693029ddebcfa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <martinroth@google.com>
2022-04-24 21:14:24 +00:00
Mattias Nissler ecc165b789 util/cbmem: add an option to append timestamp
Add an option to the cbmem utility that can be used to append an entry
to the cbmem timestamp table from userspace. This is useful for
bookkeeping of post-coreboot timing information while still being able
to use cbmem-based tooling for processing the generated data.

BUG=b:217638034
BRANCH=none
TEST=Manual: cbmem -a 1234 to append timestamp, verify that cbmem -t
shows the added timestamp.

Change-Id: Ic99e5a11d8cc3f9fffae8eaf2787652105cf4842
Signed-off-by: Mattias Nissler <mnissler@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-04-22 22:43:36 +00:00
Jianjun Wang b2537bdad5 coreboot_tables: Replace 'struct lb_uint64' with lb_uint64_t
Replace 'struct lb_uint64' with 'typedef __aligned(4) uint64_t
lb_uint64_t', and remove unpack_lb64/pack_lb64 functions since it's no
longer needed.

Also replace 'struct cbuint64' with 'cb_uint64_t' and remove
'cb_unpack64' in libpayload for compatible with lb_uint64_t.

Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: If6b037e4403a8000625f4a5fb8d20311fe76200a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-04-14 22:27:50 +00:00
Karthikeyan Ramasubramanian 4bdc2320a4 util/apcb/apcb_v3_edit.py: Edit APCB based on different SPD magic
APCB edit tool edits APCBs with LP4 specific SPDs. Introduce an option
to support different SPD magic so that the tool can be used to edit
APCBs with LP5 specific SPDs.

BUG=None
TEST=Build Skyrim board with LP5 specific SPDs. Build Guybrush board
with LP4 specific SPDs.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I8e96c89e4e5ce8e0567a17bf7685b69080fa1708
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63598
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-14 22:24:09 +00:00
Karthikeyan Ramasubramanian 58d75f80b4 util/spd_tools/part_id_gen: Support Sabrina SoC
Add support to generate DRAM part ID for boards using Sabrina SoC.

BUG=None
TEST=Generate DRAM part ID for Skyrim mainboard.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ica57b12239019831f7bf93982be3c93b7f8b6986
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-04-14 22:23:51 +00:00
Karthikeyan Ramasubramanian ad06bae7b1 util/amdfwtool: Maintain one copy of PSP Level2 entries
AMDFWtool maintains 2 copies of PSP Level2 entries - one in primary slot
A (Type 0x48) and another in backup slot B (Type 0x4A). On boards which
use VBOOT with 2 RW firmware slots, maintaining 2 copies of PSP Level2
entries in each FW slot is redundant and space-consuming. Introduce
option to maintain only one copy of PSP Level2 entries and point to it
from both slots A & B.

BUG=None
TEST=Build and boot to OS in Skyrim. Ensure that only one copy is added
to each FW slot. This achieved a space saving of 1.5 MB in each FW slot.
Before:
apu/amdfw                      0x415fc0   raw           3043328 none
After:
apu/amdfw                      0x415fc0   raw           1556480 none

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I06eef8e14b9c14db1d02b621c2f7207188d86326
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-14 15:39:15 +00:00
Zheng Bao c3007f3877 amdfwtool: Add a flag to record the second gen instead of romsig
This is for future feature combo, which gets the soc id from fw.cfg in
a loop instead of the command line, and the romsig is not set until
fw.cfg is processed.

Change-Id: Id50311034b46aa1791dcc10b107de4af6c86b927
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-13 23:25:00 +00:00