5 commits

Author	SHA1	Message	Date
Elyes HAOUAS	c3385070d6	soc/{amd,intel}/chip: Use local include for chip.h ... Change-Id: Ic1fcbf4b54b7d0b5cda04ca9f7fc145050c867b8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>	2019-04-26 16:49:13 +00:00
Kyösti Mälkki	13f66507af	device/mmio.h: Add include file for MMIO ops ... MMIO operations are arch-agnostic so the include path should not be arch/. Change-Id: I0fd70f5aeca02e98e96b980c3aca0819f5c44b98 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31691 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>	2019-03-04 15:57:39 +00:00
Kyösti Mälkki	f1b58b7835	device/pci: Fix PCI accessor headers ... PCI config accessors are no longer indirectly included from <arch/io.h> use <device/pci_ops.h> instead. Change-Id: I2adf46430a33bc52ef69d1bf7dca4655fc8475bd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>	2019-03-01 20:32:15 +00:00
Subrata Banik	834543c0c7	soc/intel/skylake: Fix ‘dev’ pointer NULL before being dereferenced ... This patch fixes KW issue due to pointer being NULL and will be dereferenced Change-Id: Iedb59daf5f448e31c0097873a086e4d08cd4a979 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/28948 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>	2018-10-08 14:49:18 +00:00
Subrata Banik	771d611f9e	soc/intel/skylake: Set low maximum temperature threshold for Thermal Device ... PMC logic shuts down the thermal sensor when CPU is in a C-state and DTS Temp <= Low Temp Threshold in case Dynamic Thermal Shutdown in S0ix is enabled. BUG=b:69110373 BRANCH=none TEST=Ensure Thermal Device(B0: D20: F2) TSPM offset 0x1c[LTT (8:0)] value is 0xFA. Change-Id: I94d09a28bf1ea07a53cfa04c54752358bafca610 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22419 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>	2017-11-30 16:27:12 +00:00