Commit graph

5 commits

Author SHA1 Message Date
Arthur Heymans
8af4fff278 mb/*/*: Add a few VBT files
These files are directly extracted from the vendor firmware.

Change-Id: I1dea2843255e4a3e93fbb734dea284be029dbc45
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26654
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-06 14:58:21 +00:00
Arthur Heymans
fd440bb79e mb/asrock/g41c-gs: Fix the SATA clock output on ck505
With reset default of the clockgen on this board the SATA clock which
needs to be 100MHz depends on FSB BSEL straps.

This explains why SATA was originally tested to be working but fails
with CPUs operating at different FSB.

This change sets a bit in the clockgen configuration which fixes the
SATA clock.

TESTED on with a 1333MHz FSB CPU.

Change-Id: Ic2b8ca91920f015ae3265871bc092023302fefdc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2017-09-22 13:09:10 +00:00
Bill XIE
1517bab693 mb/asrock/g41c-gs: Rename the board to G41C-GS R2.0 (g41c-gs_r2_0).
The supported "G41C-GS" with a nuvoton nct6776 superio is actually
G41C-GS R2.0, which is different with the more easily-found revision
G41C-GS (R1.0) with Winbond W83627DHG superio, and should be ported
separately.

Photos for the two revision:

R1.0: https://web.archive.org/web/20160915160553/http://www.asrock.com/mb/photo/G41C-GS(L1).jpg
R2.0: https://web.archive.org/web/20160717203810/http://www.asrock.com/mb/photo/G41C-GS%20R2.0(L2).jpg

Change-Id: If60a694bcf0652ab32c0ac75ceec7e27e11fe9eb
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/19980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-06-09 19:59:33 +02:00
Nico Huber
ce642f08b9 Kconfig: Rework MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG
* Rename it to HAVE_VGA_TEXT_FRAMEBUFFER.
* Let drivers select it if they are in charge.
* Don't select it on the mainboard level if a driver handles it.

Change-Id: I2d9d09be9aa6d019e77460e69a245ad2d8cda4ea
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-02 18:35:41 +02:00
Arthur Heymans
7d46e96ed7 mainboard: Add ASRock G41C-GS
Start-point is Gigabyte GA-G41M-ES2L.

This board features a G41 northbridge and an ICH7 southbridge. This
board has slots for both DDR2 and DDR3 (cannot run concurrently
though) but only DDR2 is implemented in coreboot. The SPI flash
resides in a DIP-8 socket.

Tested and working:
* DDR2 dual channel (PC2 5300 and PC2 6400, though raminit is picky
  with assymetric dimm setups);
* 3,5" IDE;
* SATA;
* PCIe x16 (with some patches up for review);
* Uart, PS2 Keyboard;
* USB, ethernet, audio;
* Native graphic init;
* Fan control;
* Reboot, poweroff, S3 resume;
* Flashrom (vendor and coreboot).

Tested but fails:
* DDR3 (not implemented in coreboot).

Tests were run with SeaBIOS and Debian sid, using Linux 4.9.0.

Change-Id: I992ee07b742dfc59733ce0f3a9be202a530ec6cc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-05-13 17:37:27 +02:00