Commit Graph

43162 Commits

Author SHA1 Message Date
Subrata Banik dbb4e4b241 soc/intel/apollolake: Make use of `cpu/intel/cpu_ids.h'
Remove inclusion of mp_init.h for getting CPUIDs and use dedicated
cpu_ids.h file in SoC directory.

Change-Id: I00ebb9a124eb3b8b893c2b176e14773c05851c18
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-17 09:51:06 +00:00
Subrata Banik 8993e67f0a soc/intel/icelake: Make use of `cpu/intel/cpu_ids.h'
Remove inclusion of mp_init.h for getting CPUIDs and use dedicated
cpu_ids.h file in SoC directory.

Change-Id: I97f4d9715f3205678acca8fcdfb1a62714dfaa53
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56375
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-17 09:50:56 +00:00
Subrata Banik a4a1e6a9b1 soc/intel/skylake: Make use of `cpu/intel/cpu_ids.h'
Remove inclusion of mp_init.h for getting CPUIDs and use dedicated
cpu_ids.h file in SoC directory.

Change-Id: I2123a081baaf6fd254fe81d64eaeee1e3248dd34
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56371
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-17 09:50:44 +00:00
Subrata Banik aec071661c soc/intel/tigerlake: Make use of `cpu/intel/cpu_ids.h'
Remove inclusion of mp_init.h for getting CPUIDs and use dedicated
cpu_ids.h file in SoC directory.

Change-Id: I773114a703d62bf469aa74b128c697cc0924cc3d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56369
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-07-17 09:50:32 +00:00
Subrata Banik 87685c5857 soc/intel/alderlake: Make use of `cpu/intel/cpu_ids.h'
Remove inclusion of mp_init.h for getting CPUIDs and use dedicated
cpu_ids.h file in SoC directory.

Change-Id: Ib62ad6a5381d346011fbc838dcd64b095fccd67b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-07-17 09:50:23 +00:00
Subrata Banik f427e8028c cpu/intel: Add dedicated file to grow Intel CPUIDs
This patch removes all local `CPUID_` macros from SoC directories and
creates a common cpu_ids.h inside include/cpu/intel/cpu_ids.h. SoC
users are expected to add any new CPUID support into cpu_ids.h and
include 'cpu/intel/cpu_ids.h' into respective files that look for
`CPUID_` macro.

Note: CPUIDs for HSW, BDW and Quark are still inside the respective
directory.

Change-Id: Id88e038c5d8b1ae077c822554582410de6f4a7ca
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-07-17 09:50:14 +00:00
Subrata Banik 647a7bb777 soc/intel/xeon_sp/cpx: Align Cooper Lake CPUID as per EDS
This patch removes leading zero from CPUIDs as below:
0x05065a -> 0x5065a
0x05065b -> 0x5065b

Change-Id: I240a06e3b3d7e3dc080f9a9ed1539fadc982495d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-07-17 09:49:49 +00:00
Felix Singer f7100eb1c9 mb/google/volteer: Deduplicate lockdown config
The setting `chipset_lockdown` has the same configuration for all
variants and they also match with the baseboard configuration. Thus,
remove it from the variant overridetrees.

Built google/delbin with `BUILD_TIMELESS=1` and coreboot.rom
remains the same.

Change-Id: I597e4487e7a0e1848d2a2f2c8f8ebd552994aac2
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56199
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-17 00:10:21 +00:00
Felix Singer 5f235b0a3f mb/google/volteer/baseboard: Configure chipset_lockdown separately
The configuration of the setting `chipset_lockdown` doesn't have any
effect for most of the variants since their configuration of
`common_soc_config` overwrites the configuration of the baseboard's
devicetree. If `chipset_lockdown` is configured separately in the
baseboard devicetree, the variant overridetrees reuse its
configuration.

Thus, move `chipset_lockdown` out of `common_soc_config` in the
baseboard devicetree and configure it separately.

Change-Id: I595c042cf62680d61f60965710d382bfdcd81671
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56209
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-17 00:10:08 +00:00
Felix Held ea192f86c9 mb/google/kahlee/Kconfig: add board-specific MAINBOARD_PART_NUMBER
Before the part number for all boards was "Grunt". This patch adds the
correct part number/name for all variants.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If506df0b1027fb09f5027d8b9653b776fe3bdc75
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55681
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-16 20:59:56 +00:00
FrankChu a1b5a6295c mb/google/volteer/variants/collis: Redefine GPIO_EC_IN_RW to GPP_F17
Redefine GPIO_EC_IN_RW to GPP_F17

BUG=b:193091165
BRANCH=firmware-volteer-13672.B
TEST=verify FAFT firmware_DevMode Pass

Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I24f4803dc99ef3fc78852241f3a9e86ec70293d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-07-16 18:07:07 +00:00
Felix Held f1e8e7f148 include/cpu/amd/msr: don't redefine the IA32_BIOS_SIGN_ID MSR
Change-Id: Iff19ae495fb9c0795dae4b2844dc8e0220a57b2c
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-07-16 14:10:07 +00:00
Yu-Ping Wu 1ce645347c mb/google/cherry: Allow payloads to enable USB VBUS
Configure GPIO DGI_D4 (AP_XHCI_INIT_DONE) as output, so that payloads
(for example depthcharge) can assert it to notify EC to enable USB VBUS.

BUG=b:193499785
TEST=emerge-cherry coreboot
BRANCH=none

Change-Id: I21b7b811b8138cb3f71efecb0a0a886905c65a9c
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-07-16 04:15:53 +00:00
Maxim Polyakov 9941e5a5e6 ec/kontron/kempld: Add minimal GPIO driver
The patch adds an interface for configuring GPIOs inside the Kontron
CPLD/EC. This allows to statically define the mode for each GPIO pin
in devicetree.cb of the motherboard or carrier board. For example:

chip ec/kontron/kempld
	device gpio 0 on
		register "gpio[0]"  = "KEMPLD_GPIO_INPUT"
		register "gpio[4]"  = "KEMPLD_GPIO_OUTPUT_LOW"
		register "gpio[5]"  = "KEMPLD_GPIO_OUTPUT_HIGH"
		register "gpio[11]" = "KEMPLD_GPIO_DEFAULT"
	end
end

In this case, <device gpio 0>, like all other devices, is not a real
device inside the EC. These definitions are used to understand the EC
resources and systematize configuration options, but if mark this as
<off>, the initialization step will be skipped in the driver code.

Use KEMPLD_GPIO_DEFAULT or skip it in devicetree.cb to not configure
the GPIO and keep the default mode after CPLD reset.

This work is based on code from the drivers/gpio/gpio-kempld.c linux
driver. Tested on Kontron mAL-10 COMe module [1].

[1] CB:54380 , Change-Id: I7d354aa32ac8c64f54b2bcbdb4f1b8915f55264e

Change-Id: Id767aa451fbf2ca1c0dccfc9aa2c024c6f37c1bb
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47595
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-16 04:12:36 +00:00
Raul E Rangel 000138e6c1 lib/thread: Verify threads are initialized before yielding
In hardwaremain.c we call console_init before threads_initialize. Part
of setting up the uart requires calling udelay which then calls
thread_yield_microseconds. Since threads have not been set up, trying to
yield will result in bad things happening. This change guards the thread
methods by making current_thread return NULL if the structures have not
been initialized.

BUG=b:179699789
TEST=Ramstage no longer hangs with serial enabled

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: If9e1eedfaebe584901d2937c8aa24e158706fa43
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56318
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-15 21:50:27 +00:00
Julian Schroeder 577e146895 soc/amd/cezanne: add ACPI CPPC support for AMD
This leverages the existing Collaborative Processor Performance Control
(CPPC) support and adds CPPC init for AMD/Cezanne.

BUG=b:185814875
TEST=under Linux/ChromeOS, acpidump ssdt2, find expected CPPC entries

Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com>
Change-Id: I94172f40c7fa4b7b89237fd382448e598da00fbb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-07-15 21:39:04 +00:00
Felix Held 82e2f3229e soc/amd/common/block/cpu/mca/mcax: print all MCAX registers
Also move the registers in the order they are in the hardware.

Change-Id: If018e746e58c14475caeda76feb8b5281d7732f1
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56315
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-15 18:17:42 +00:00
Felix Held ae4f0ceb88 soc/amd/common/block/cpu/mca: make building the BERT support conditional
Only when ACPI_BERT is selected the BERT functionality needs to be
included in the build.

Change-Id: I8a21562f4535fb0ea3c53f2ea8df50f66cc6a64c
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56314
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-15 17:36:51 +00:00
Felix Held bb0af23868 soc/amd/common/block/cpu/mca: commonize mca_check_all_banks
Since we don't need to skip the MCA check on cold boot on MCAX capable
systems, add a mca_skip_check implementation that always returns false.

Change-Id: Id8fc4b6f02b6c02b03172fe11f0451a9893e514d
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-15 17:36:40 +00:00
Felix Held b97f953fcc soc/amd/common/block/cpu/mca/mca: factor out mca_skip_check
This will allow moving mca_check_all_banks to mca_common.c.

Change-Id: I58e100c1447907bab984a2fdff6c6e0181910c23
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-15 17:04:51 +00:00
Felix Held d1d6479ddf soc/amd/stoneyridge/mca: implement and use mca_has_expected_bank_count
This aligns the mca_check_all_banks implementation in the common mca.c
with the one in the common mcax.c file. Do the MCA bank count check
before the !is_warm_reset() check, so that a mismatch also gets printed
on the cold boot path.

Change-Id: Idbd3e9ce9c7483f84f87adab7adac47335cd59aa
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-15 17:04:28 +00:00
Felix Held 5ce2751d6d soc/amd/common/block/cpu/mca: move function prototypes to local header
Since those functions are implemented and used only inside the common
MCA(X) code, there's no need to have them in the header file that gets
included in the SoC-specific code.

Change-Id: Ia84e149d67ac7d80de595379c73a6cf08730719d
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-15 17:03:54 +00:00
Felix Held e84c3f1898 soc/amd/*/mca: factor out common MCA/MCAX check & print functionality
For Cezanne stubs are added for the functions that the SoC-specific code
needs to provide. Since the mca_is_valid_bank stub on Cezanne always
returns false, the checks get skipped for it at the moment. The actual
functionality will be added in a later patch.

Change-Id: Ic31e9b1ca7f8fac0721c95935c79150d7f774aa4
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-15 17:03:30 +00:00
Felix Held 64077de176 soc/amd/picasso/mca: factor out mca_has_expected_bank_count
To factor out the rest of the common MCAX code, mca_bank_name[] may only
be accessed by accessor functions, so implement this for the last place
that still accessed mca_bank_name[] directly.

Change-Id: Ic6548d3ceeb9c00ad344fc0bb3d97893e17a43a9
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56294
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-15 16:55:47 +00:00
Felix Held a83a58fe62 soc/amd/common/blocks/cpu/mca: factor out common BERT helper functions
Change-Id: I03365c3820cbe7277f14adc5460e892fb8d9b7a5
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56284
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-15 16:55:20 +00:00
Felix Held 2ecf1561b4 soc/amd/*/mca: factor out BERT entry generation to soc/amd/common
Change-Id: I960a2f384f11e4aa5aa2eb0645b6046f9f2f8847
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56283
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-15 16:54:47 +00:00
Maulik V Vaghela 63e34c4d34 soc/intel/alderlake: Add virtual GPIOs for community 1
Alder Lake SoC has virtual GPIOs for community 1 which was being
programmed by FSP and hence was skipped by coreboot. As part of
moving most of the GPIO programming to coreboot, we're skipping this
programming in FSP now.

TEST=Check register offset to see if programming is correct.

Change-Id: I4d48553d14465df50e5aaaf27ab26c6a1b70d4cf
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55270
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-15 14:07:20 +00:00
Julius Werner df5062215f drivers: spi_flash: Add Fast Read Dual I/O support
The Fast Read Dual Output and Fast Read Dual I/O commands are
practically identical, the only difference being how the read address is
transferred (saving a whooping 2 bytes which is totally irrelevant for
the amounts of data coreboot tends to read). We originally implemented
Fast Read Dual Output since it's the older command and some older
Winbond chips only supported that one... but it seems that some older
Macronix parts for whatever reason chose to only support Fast Read Dual
I/O instead. So in order to make this work for as many parts as
possible, I guess we'll have to implement both. (Also, the Macronix
device ID situation is utter madness with different chips with different
capabilities often having the same ID, so we basically have to make a
best-effort guess to strike a trade-off between fast speeds and best
chance at supporting all chips. If this turns out to be a problem later,
we may have to add Kconfig overrides for this or resort to SFDP parsing,
although that would defeat the whole point of trying to be fast.)

BUG=b:193486682
TEST=Booted CoachZ (with Dual I/O)

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ia1a20581f251615127f132eadea367b7b66c4709
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-07-15 14:05:34 +00:00
Julius Werner 825693a3d5 google/trogdor: Enable SPI_FLASH_MACRONIX
We may want to use that flash vendor on future variants.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I2c0fa87fd3f8de8f928e5f41eae2a78204597b5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-07-15 14:04:44 +00:00
Meera Ravindranath 92637df79a drivers/intel/gma: Restructure Opregion version info code
Define a structure for opregion version information to align
with spec/kernel.

BUG=b:190019970
BRANCH=None

Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I93a9f2df186002a4e38caa910f867bce0b97ac2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-15 14:04:11 +00:00
Subrata Banik 7d3e57d7a3 soc/intel/tigerlake: Use `is_devfn_enabled()` for Crashlog UPDs
Enable FSP Crashlog UPDs if SA_DEVFN_TMT is enabled and
SOC_INTEL_CRASHLOG is selected by the SoC user.

Change-Id: Ibcd0259da86c8d9853e6cc4983675ac97df46c2d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56299
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-15 14:03:57 +00:00
Subrata Banik 7b8d11b186 soc/intel/alderlake: Use `is_devfn_enabled()` for Crashlog UPDs
Enable FSP Crashlog UPDs if SA_DEVFN_TMT is enabled and
SOC_INTEL_CRASHLOG is selected by the SoC user.

Change-Id: I0244e2a3f9c000a5c6ecdade1419aa47f51b1e80
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56298
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-15 14:03:40 +00:00
Monika A c06aa3ac22 mb/intel/adlrvp: Disable xDCI in devicetree
Disable tcss_xdci as it is not used.

Signed-off-by: Meera Ravindranath  <meera.ravindranath@intel.com>
Change-Id: I94102240b13d2b96e0295f41bc2b0ba078faf342
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52262
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2021-07-15 14:02:45 +00:00
Martin Roth 48d6717573 mb/google/guybrush: Make VBOOT_STARTS_BEFORE_BOOTBLOCK a default
To be able to enable & disable PSP_verstage in the saved .config file,
the symbol VBOOT_STARTS_BEFORE_BOOTBLOCK needs to be changed from a
select to a default with a prompt.

BUG=182477057
TEST=Build, get PSP_verstage, disable VBOOT_STARTS_BEFORE_BOOTBLOCK,
verify that VBOOT_STARTS_IN_BOOTBLOCK is set.

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Iba735f33f9b079c9868ef2fff099c5298ff72b6a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56289
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-15 14:02:32 +00:00
Subrata Banik 6da003c910 util/ifdtool: Add APL to IFDv2 platforms
Initially APL was considered as IFDv2 platform irrespective being
added into ifd_2_platforms[], hence commit hash 621ed4c had migrated
APL into IFDv1 which break its FLMSTR1/FLMSTR2/FLMSTR3 Read/Write
access. This change adds APL into the list of IFDv2 platforms to fix
booting issue on the LeafHill board.

Change-Id: Ied59ddb2fe05b421266a6b119fd6eab17b8beedc
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56300
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rick Lee <rick.lee@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-15 04:25:27 +00:00
Felix Held e0d9bf7731 soc/amd/picasso/mca: add missing types.h include
Change-Id: I67a88298c19657a5049ab69799be887555ca7240
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-07-14 23:11:01 +00:00
Felix Held 1e1d490ff8 soc/amd: factor out check_mca to common code
Change-Id: I139d1fe41bad5213da8890c2867f275b6847e3e1
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56281
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14 23:10:46 +00:00
Felix Held dc970fc039 soc/amd/cezanne/mca: add empty mca_check_all_banks function
This will allow factoring out and moving check_mca() to soc/amd/common.

Change-Id: I92c7657baef17c248a5aef1eda268e9647502837
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56280
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14 21:59:24 +00:00
Felix Held f1093af1f6 soc/amd: move check_mca prototype to soc/amd/common/blocks/include
Change-Id: Ia489dbfba59c334cf29f96a4000cef73b9b797d4
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56279
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14 21:58:59 +00:00
Felix Held 65deb24a8e soc/amd/stoneyridge: add and use mca_is_valid_bank & mca_get_bank_name
This patch changes the way how the not implemented MCA bank 3 gets
skipped. For the not implemented bank 3 the name gets set to NULL
resulting in mca_is_valid_bank returning false causing the bank to get
skipped. This is a preparation for commonizing the MCA(X) handing in the
soc/amd sub-tree.

Change-Id: I40d6a6752504d804c45b445fce7e763e80161211
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-14 21:58:27 +00:00
Felix Held b04148aa56 soc/amd/picasso: implement and use mca_get_bank_name
Change-Id: I42abff5efcd7c85d2932a7aaacc736d0376cfaa0
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56276
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-07-14 21:57:32 +00:00
Felix Held 040d7646bc soc/amd/picasso: implement and use mca_is_valid_bank
In mca_check_all_banks only check valid MCA banks for errors. This
aligns the Picasso code a bit more with the Stoneyridge code base which
will be updated in a follow-up patch. This is a preparation for
commonizing the MCA(X) handing in the soc/amd sub-tree.

Change-Id: I0c7f3066afd220e6b8bf8308a321189d7a2679f6
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56275
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14 21:56:24 +00:00
Felix Held 07ad2d9439 soc/amd/picasso: check length of mca_bank_name array
The length of mca_bank_name should match the return value of
mca_get_bank_count which gets the number of MCA banks from an MSR.

TEST=No error message on serial console on amd/mandolin

Change-Id: Ibdad51a7ef27266e110dfbb43188361952618342
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56274
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14 21:55:57 +00:00
Felix Held 799742af3d soc/amd/picasso: add missing banks to mca_bank_name array
Also use array indices for the initialization.

TEST=Checked with the public Picasso PPR #55570-B1 Rev 3.16

Change-Id: I10a65210da73e64b67d613609fcc0f9a245a81fb
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56273
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14 21:55:30 +00:00
Angel Pons dd405bc018 drivers/usb/acpi: Avoid dereferencing maybe-NULL pointer
Do not dereference a pointer before checking whether it is NULL.

Change-Id: Icbe9ae99d91fd587d8e56cf3a0dcb59834ee6d07
Found-by: Coverity CID 1458232
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56266
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14 21:26:47 +00:00
Angel Pons afab34c372 drivers/usb/acpi: Replace unneeded `memcpy` use
A regular assignment works just as well and also allows type-checking.
It also avoids a common mistake where `sizeof` is applied to a pointer
to obtain the size of the data it points to, without dereferencing it.

Found-by: Coverity CID 1458231
Change-Id: I7ed05322c3c911f3da4145f81e4d9760a275fec2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56265
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14 21:26:34 +00:00
Kangheui Won 275ade9539 Revert "amdfwtool: Use relative address for EFS gen2"
This reverts commit 0fc87e31e0.

Reason for revert: Breaks psp_verstage in guybrush

BUG=b:182477057

Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: Ie50cba4aaf31425ef8fee848c098a826f55c98da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56131
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14 20:45:10 +00:00
Felix Held a0112c12c8 soc/amd/stoneyridge: use index for mca_bank_name initialization
Change-Id: Id640fd8006c47ce1db8a8729407c1c9a9c1e79c3
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56272
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14 20:38:21 +00:00
Felix Held e4a6edf599 soc/amd/stoneyridge/mca: add missing types.h include
Change-Id: Ifbcad4d81fb9f6c359a870be73b05ed86441e7f0
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56271
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14 20:27:16 +00:00
Martin Roth 679c37aa8d src/device: Remove DEVICE_PATH_ESPI & DEVICE_PATH_LPC
The ESPI & LPC keywords were added for the zork program, but it was
found that they weren't needed, so they were never used.  The previous
patch removes them from sconfig, so now they aren't needed in coreboot.

BUG=None
TEST=Build

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I9ae7817bb63d69ee272103b2d1186f125e188950
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56278
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14 20:24:12 +00:00