Commit Graph

13617 Commits

Author SHA1 Message Date
York Yang c13ad6c6df driver/intel/fsp: Correct the fastboot data (MRC data) printing length
Fastboot data in Intel FSP project is printed by hexdump32() in dword
length. So the data length needs to be divided by 4 when printing it.

Change-Id: I959d538bd6e60282882dd138045cc730b4bd8159
Signed-off-by: York Yang <york.yang@intel.com>
Reviewed-on: http://review.coreboot.org/9976
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-24 21:15:41 +02:00
Alexandru Gagniuc 11004878ce Revert "board-status: Add field for release year"
This reverts commit d555d5a2b5.

It produces too much clutter, and is not particularly useful.

Change-Id: I62268a215a22a5cc76a10cdcfcae86349b466963
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/9990
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: Patrick Georgi <pgeorgi@google.com>
2015-04-24 18:15:08 +02:00
Patrick Georgi d555d5a2b5 board-status: Add field for release year
Add the option to add a release year to each mainboard to
get a sense of how old the hardware is.

Change-Id: Id43c80fdf8bf65241b2be92678616d1774529f8c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/9945
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2015-04-24 09:20:04 +02:00
Marc Jones 786879777a fsp: Move fsp to fsp1_0
Prepare for FSP 1.1 integration by moving the FSP to a FSP 1.0 specific
directory. See follow-on patches for sharing of common code.

Change-Id: Ic58cb4074c65b91d119909132a012876d7ee7b74
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/9970
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-24 00:37:37 +02:00
Aaron Durbin be34797e4c ramstage: don't drop cbmem console
In commit b0d8f5e9 I moved the call to cbmem_initialize()
in the CONFIG_EARLY_CBMEM_INIT case to the very beginning of
ramstage. However, that caused an issue in the ordering of the
cbmem console driver in that it expects cbmemc_init() to be
called prior to cbmemc_reinit(). Therefore, ensure console
is called as the first thing even if some time is lost w.r.t.
timestamp tracking.

Change-Id: I42137d28116e0bccb9235f4e3f394d4fd8b84e37
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9933
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-23 16:35:51 +02:00
Aaron Durbin d70bf7cc21 cbmem_console: fix it for x86
The Kconfig options pertaining cbmem console in the preram
environment no longer make sense with the linker script
changes. Remove them and their usage within cbmem_console.

Change-Id: Ibf61645ca2331e4851e748e4e7aa5059e1192ed7
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9851
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-23 16:35:51 +02:00
Patrick Georgi 58decc540d memlayout: Make sure preram_cbmem_console symbols exist
This enables its _size variable (a macro) to work even when
the console has no location assigned to it in the chip/board's
memlayout.ld.
Since _size == 0, the code will do the right thing.

Change-Id: I6b42ed0c5c3aaa613603680728b61cbdb24c4b61
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9973
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-23 16:34:00 +02:00
Mathias Friman a52f9033df src/mainboard/*/*/board_info.txt: Added Release year for boards
To simplify browsing the "Supported hardware" list, I added Release year
for the hardware from asus, asrock, gigabyte, msi, via, tyan, intel,
lenovo, apple, jetway and hp. Still several models and manufacturers to
add information to. This is more of a proof-of-concept.
The "Release year" will be shown in the wiki page.

Change-Id: I6bc14ed06ac7c6b3c9f054b49f08cb9b3dc47947
Signed-off-by: Mathias Friman <mathias@workplays.se>
Reviewed-on: http://review.coreboot.org/9963
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-04-23 14:42:44 +02:00
Bruce Griffith 72645bbd67 AMD Lamar: Add a new AMD FP3 socket mainboard
Add a new mainboard based on AMD's Family 15 Model 30 processor.
TEST: Lamar will boot DOS, Ubuntu 14.10 and Windows 7.

Change-Id: I2f73c396247239d54f978846e8958950697d7464
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/5968
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-23 00:58:26 +02:00
Aaron Durbin 0dff57dd7a cbmem: switch over to imd-based cbmem
By design, the imd library still provdes dynamic growth so that
feature is consistent.  The imd-based cbmem packs small allocations
into a larger entry using a tiered imd. The following examples show
the reduced fragmentation and reduced memory usage.

Before with dynamic cbmem:
CBMEM ROOT  0. 023ff000 00001000
aaaabbbb    1. 023fe000 00001000
aaaabbbc    2. 023fd000 00001000
aaaabbbe    3. 023fc000 00001000
aaaacccc    4. 023fa000 00002000
aaaacccd    5. 023f9000 00001000
ROMSTAGE    6. 023f8000 00001000
CONSOLE     7. 023d8000 00020000
COREBOOT    8. 023d6000 00002000

After with tiered imd:
IMD ROOT    0. 023ff000 00001000
IMD SMALL   1. 023fe000 00001000
aaaacccc    2. 023fc000 00001060
aaaacccd    3. 023fb000 000007cf
CONSOLE     4. 023db000 00020000
COREBOOT    5. 023d9000 00002000
IMD small region:
  IMD ROOT    0. 023fec00 00000400
  aaaabbbb    1. 023febe0 00000020
  aaaabbbc    2. 023feba0 00000040
  aaaabbbe    3. 023feb20 00000080
  ROMSTAGE    4. 023feb00 00000004

Side note: this CL provides a basis for what hoops one needs to
jump through when there are not writeable global variables on
a particular platform in the early stages.

Change-Id: If770246caa64b274819e45a26e100b62b9f8d2db
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9169
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-22 22:56:31 +02:00
Patrick Georgi cfba6099d6 elog: enable by default for CHROMEOS
elog breaks the build if ELOG_FLASH_BASE isn't configured -
and CHROMEOS isn't enabled, since with Chrome OS builds, it
just uses fmap to find out the base.

So it makes sense to enable it on all Chrome OS builds - if
the code never uses it, the linker will drop it soon enough.

Change-Id: I7ee129fadf75caf15fb9bd32b0acf6f7d9d015d8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9965
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22 22:25:40 +02:00
Vadim Bendebury 6897f4e796 google/storm: indicate start of normal boot on LED ring
Instead of switching off the LED ring for the normal boot path, turn
it on with the dedicated pattern, indicating that the device firmware
has started executing.

BRANCH=storm
BUG=chrome-os-partner:39044
TEST=program the new firmware on an SP5 device and verify that the new
     'normal boot' pattern is displayed in all following scenarios:

 - power up the device (the pattern shows within the first second)

 - boot the device to bash prompt and restart.

 - press the recovery button and reboot the device. Once the LED ring
   shows the 'recovery button pressed' pattern, release the recovery
   button.

Change-Id: Iedd66d2575ad587af77e35d23efb22a83a92858b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 092358bd17a323d0bd2fec555f43cb587486bbec
Original-Change-Id: I24de45326eab83b57bcf16b5598388f81c7d0f00
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/265536
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9923
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-04-22 20:01:24 +02:00
Vadim Bendebury ace3e3fc5e i2c/ww_ring: add a pattern for normal boot
It became necessary to indicate the beginning of the normal boot
process. This patch adds a new pattern, a slow (over 2 seconds) fade
in into the 0, 87, 155 color.

BRANCH=storm
BUG=chrome-os-partner:39044
TEST=tested by the next patch.

Change-Id: Idd977688e5aa2cc55fc295072c0766526ae95016
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 577c8bd6f8c69073cfdd7acd4a87e7ae603d48e6
Original-Change-Id: I9aff3f4558e733ff2e47206075533556e400f183
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/265535
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9922
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22 20:01:15 +02:00
Deepa Dinamani a386bf790e google/storm: enable zero page access protection.
BRANCH=storm
BUG=chrome-os-partner:24786
TEST=verified mmu.pagetable.list output for Storm:
 _______address___________|_physical________________|sec|_d_|_size____|_permissions____________________|_glb|_shr|_pageflags______________________|
      C:00000000--00000FFF|                         |   |   |         |                                |    |    |                                |
      C:00001000--000FFFFF|  A:00:00001000--000FFFFF| ns| 00| 00001000| P:readwrite U:readwrite notexec| yes| no | strongly ordered               |
      C:00100000--29FFFFFF|  A:00:00100000--29FFFFFF| ns| 00| 00100000| P:readwrite U:readwrite notexec| yes| no | strongly ordered               |
      C:2A000000--2A05FFFF|  A:00:2A000000--2A05FFFF| ns| 00| 00001000| P:readwrite U:readwrite exec   | yes| no | write-back/no write alloc      |
      C:2A060000--2A0FFFFF|  A:00:2A060000--2A0FFFFF| ns| 00| 00001000| P:readwrite U:readwrite notexec| yes| no | strongly ordered               |
      C:2A100000--3FFFFFFF|  A:00:2A100000--3FFFFFFF| ns| 00| 00100000| P:readwrite U:readwrite notexec| yes| no | strongly ordered               |
      C:40000000--59FFFFFF|  A:00:40000000--59FFFFFF| ns| 00| 00100000| P:readwrite U:readwrite exec   | yes| no | write-back/no write alloc      |
      C:5A000000--5A1FFFFF|  A:00:5A000000--5A1FFFFF| ns| 00| 00100000| P:readwrite U:readwrite notexec| yes| no | strongly ordered               |
      C:5A200000--7FFFFFFF|  A:00:5A200000--7FFFFFFF| ns| 00| 00100000| P:readwrite U:readwrite exec   | yes| no | write-back/no write alloc      |
      C:80000000--FFFFFFFF|                         |   |   |         |                                |    |    |                                |

Change-Id: I08a5094b2da9d67244c94984e2da14399e477b01
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f137a589434b09055e6b9d32907e662e6c296502
Original-Change-Id: Ia2deab1cf8f08c4ba5a5b6dbe4c4ebf29c9df480
Original-Signed-off-by: Vikas Das <vdas@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/253801
Original-Tested-by: Deepa Dinamani <deepad@codeaurora.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Deepa Dinamani <deepad@codeaurora.org>
Reviewed-on: http://review.coreboot.org/9920
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22 20:00:08 +02:00
Vadim Bendebury f96c7c7211 i2c/ww_ring: update color definitions
After testing on a final assembly the PD team adjusted the wipeout
request and recovery request modes' colors.

BRANCH=storm
BUG=none
TEST=verified new colors while booting an SP5 device in recovery mode

Change-Id: I9bd2dac63b99140573533c2cda8eaa9213478ab1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 41c34a619dc0317af67907f18ee844c71a73d623
Original-Change-Id: Iab84710ebdeed35ddd4a8a163bbb6b8ac9cdb799
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/262602
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9890
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22 19:58:44 +02:00
Vadim Bendebury 8ac8ffa318 i2c/ww_ring: change colors for different display modes
Modify colors as suggested by product review folks. This is not final,
to make it easier to identify RGB locations in the hex dumps, express
their values in decimal as opposed to hex.

BRANCH=storm
BUG=chrome-os-partner:36059
TEST=verified new all three color schemes while pressing the recovery
     button at boot for 20 seconds.

Change-Id: I7461acd7004e3d10cba6665a9bfe25ec8aa6f3ba
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7a075824a1954eb5d1b65ce887304924724a6d21
Original-Change-Id: I7f5968e361333572fd1f84aa11b7150194ad902a
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/261690
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9880
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22 19:58:34 +02:00
Vadim Bendebury 3a7290bc91 storm: add config option to clear dev mode state on recovery
Storm and whirlwind devices should leave developer mode as soon as
recovery is requested.

BRANCH=storm
BUG=chrome-os-partner:36059
TEST=with the rest of the patches applies observed desired behavior on
     SP5

Change-Id: I3e8e481f85cd067eff4fe2049b8aa47e09f6d63e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c6dbafc16edb11ec687359b25098ce8a1b055b91
Original-Change-Id: Iac6fa62229556bc7a6960d7f1630d37570ba72c4
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/261621
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9879
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22 19:58:14 +02:00
Vadim Bendebury f9c0e20e68 google/storm: enable virtual development mode switch
The whirlwind device is using a button instead of the switch to enable
dev mode.

BRANCH=storm
BUG=chrome-os-partner:36059
TEST=with the rest of the patches applied it is possible to enable and
     disable dev mode on Whirlwind and the mode persists over reboots.

Change-Id: I6d31c8429ea0515bea2b7d707325d9092487048a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 495bd07e3a1d6c587a5f01efa2801d2c4e7edbe8
Original-Change-Id: I8879833ca13074e8275393c3b98df06d56a5361d
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/261416
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9875
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22 19:57:55 +02:00
Vadim Bendebury 89994226e8 i2c/ww_ring: use shorter blinking program
The originally loaded blinking program was written to allow gradual
change in LED brightness, which required controlling each LED with its
own engine. In fact there is no need in gradual brightness changes
when the firmware is controlling the ring. This allows to control all
LEDs by one engine, making the code simpler and more robust (no need
to synchronize the three engines any more).

BRANCH=storm
BUG=chrome-os-partner:36059
TEST=verified that recovery boot WW ring patterns work as expected.

Change-Id: I89d231fb61693f4e834d8d9323ae5a7ddd149525
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 19809cf8120df8865da9b5b9e7b8e932334bf4b5
Original-Change-Id: I41038fd976dc9600f223dc0e9c9602331baf68f9
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/261026
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9873
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22 19:57:37 +02:00
Vadim Bendebury 420fb5eb3e i2c/ww_ring: stop running programs before loading the new ones
The two controllers on the ring are programmed independently, and if
the second controller is running the old pattern while the first one
was loaded with a new pattern, there is a window of when the two
unrelated patterns might interact.

To avoid this shut down execution on both controllers before starting
downloading the new pattern code.

BRANCH=storm
BUG=chrome-os-partner:36059
TEST=verified recovery/wipeout LED ring behavior did not change.

Change-Id: I163f2983d414fe839208054ae3e9025663a46aeb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3502ca6b119c033855b45388e7b782d35cfdd82b
Original-Change-Id: I0f71f94a7e82f6c0e7f98d3aad1f93ece207248f
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/261200
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9872
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22 19:57:28 +02:00
Vadim Bendebury 5fa5f99d47 i2c/ww_ring: define display pattern programs
Add compiled lp55231 code snippets to allow display certain patterns
when booting the device with the recovery button pressed.

As soon as the press is detected, the low intensify solid white
pattern is enabled. Holding recovery button long enough causes the
device transition between the wipeout requested and recovery requested
states, with the appropriate changes in the displayed pattern.

The patch also includes the source code for the LED controller as well
as instructions on how to compile and modify the code to result in
different colors, intensities, blink periods and duty cycles.

BRANCH=storm
BUG=chrome-os-partner:36059
TEST=reboot an SP5 device with the LED ring attached, keep the
     recovery button pressed, observe the changes in the LED display
     pattern while the device progresses through the boot sequence.

Change-Id: Ic7d45fc7c313b6d21119d4ae6adaeb4f46f7d181
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0fd6a5c0067d705197816629f41640a931d2f7cd
Original-Change-Id: Ib5cc5188c2eeedbba128101bf4092a0b9a74e155
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/260670
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9870
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22 19:55:34 +02:00
Vadim Bendebury 4e0de324eb i2c/ww_ring: decouple LED display from vboot
The patterns displayed on the LED ring while under the coreboot
control are not driven by the vboot, but by the board code instead,
The four distinct states of the LED display are:
  - all off
  - recovery button push detected, waiting for it to be released
  - wipeout request pending - recovery button was pushed long enough
    to trigger this request
  - recovery request pending - recovery button was pushed long enough
    to trigger this request.

BRANCH=storm
BUG=chrome-os-partner:36059
TEST=no functional changes

Change-Id: I38d9a3028013b902a7a67ccd4eb1c5d533bf071c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bdfff0e646283da6a2faaacf33e0179d2fea221c
Original-Change-Id: Ie279151b6060a2888268a2e9a0d4dc22ecaba460
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/260649
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9868
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22 19:54:17 +02:00
Vadim Bendebury 507a0cbff8 i2c/ww_ring: various driver fixes and improvements
When in development environment, some SP5 devices might not have the
LED ring attached. They are still fully functional, but when booting
up are generating massive amount of i2c error messages. This patch
prevents accesses to non-existing lp55321 devices.

When loading the program into the device the vendor recommends 1 ms
delay when accessing the program control register. This patch
separates these accesses into a function and add a delay after every
access.

Another fix - advance the program address when loading multipage
programs.

Set the global variable register 3c, not used by coreboot programs, to
a fixed value. This will allow depthcharge to avoid re-initializing
the controller when not necessary.

BRANCH=storm
BUG=chrome-os-partner:36059
TEST=booted firmware on an SP5 with no LED ring attached, no excessive
     error messages are generated, saw the default pattern displayed
     when the recovery button is pressed during reset.

Change-Id: I6a2a27968684c40dae15317540a16405b1419e30
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5e0b4c84aca27460db594da1faf627ddee56f399
Original-Change-Id: I10f1f53cefb866d11ecf76ea48f74131d8b0ce77
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/260648
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9867
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22 19:53:42 +02:00
Vadim Bendebury 381785df45 google/storm: support factory reset (wipeout) request
The recovery switch on storm is overloaded: it needs to be pressed for
a certain duration at startup to signal different requests:

  - keeping it pressed for 8 to 16 seconds after startup signals the need for
    factory reset (wipeout);
  - keeping it pressed for longer than 16 seconds signals the need for Chrome
    OS recovery.

This patch adds a function to report the wipeout request status and
enables the new feature on Storm.

BRANCH=storm
BUG=chrome-os-partner:37219

TEST=verified that keeping the recovery button pressed between 8 and
     16 seconds at startup results in the wipeout request generated
     (crossystem 'wipeout_request' returns 1). Keeping the button
     pressed for more than 16 seconds triggers recovery mode.

Change-Id: I17131593e12833866a22837271feb0e6989e6750
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3c503ec13c2b096d4a21fb299c0dd0396f1d01e9
Original-Change-Id: Ic3678217906e56307d47378fa8a6defeb314084e
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/259844
Reviewed-on: http://review.coreboot.org/9863
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-04-22 19:53:13 +02:00
Vadim Bendebury 8a6e635419 google/storm: use whirlwind LED ring on SP5 boards
The latest whirlwind requirements call for the need to indicate
different device states while it is still in coreboot (it could be
waiting for recovery or for factory reset trigger).

Initialize the LED ring when running on the SP5 hardware (which is the
first proper Whirlwind device).

BRANCH=storm
BUG=chrome-os-partner:36059
TEST=when the device starts the LED ring gets shut down

Change-Id: I9dd0bca4849a2a8500322c84c7351aeef00d862e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 24e4da56d4c43d03f235d0cfd5995ef235e6a2c5
Original-Change-Id: Ica37301aa27f35897d2bf467ae319fb5e68adc1d
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/258271
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9859
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22 19:52:58 +02:00
Vadim Bendebury 71558f5627 i2c: add support for ww_ring
This is a copy of the depthcharge ww ring driver implementation ported
into coreboot. The main differences are:

 - direct use of the i2c driver instead of using the callback driver
   description

 - no dynamic memory allocation for the controller structures

BRANCH=storm
BUG=chrome-os-partner:36059
TEST=with the rest of the patches applied the LED ring gets
     initialized to the default pattern at coreboot start.

Change-Id: I6902c8b76fc173ad2ec28b8cc94695e892df338a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: eda24b78f8aff311dd6296d458bdfecf26c3d65a
Original-Change-Id: I5660dc3f255aab8fbe3a87041c72916a645c193b
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/257730
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9858
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22 19:52:51 +02:00
Patrick Georgi dd78736d4e abuild: add option to build with CHROMEOS enabled
abuild -x (we're running out of letters) builds with CHROMEOS enabled.

Change-Id: Ie9abd8aa999dd339aab113ff28c16671b2a17845
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9966
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22 19:37:01 +02:00
Patrick Georgi 8bf5c15f76 abuild: mark failed builds as failed
abuild only created compile.status for successful builds,
but sometimes it's helpful to easily identify all failed
builds of a full run:

$ grep -l failed coreboot-builds/*/compile.status

Change-Id: Ic90280fb2e8cff1f8f558a2e67ffad741beddbdf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9964
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-04-22 19:36:36 +02:00
Patrick Georgi 392e9b156e util/broadcom: specify libraries after object files
Some compilers and linkers require a strict order or fail to find
all symbols.

Change-Id: I3f44bec1f0e21e7313a751fbc99c61c1aa9b7cf1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9962
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22 19:36:29 +02:00
Patrick Georgi a1361d4318 mainboards: Add CHROMEOS_VBNV_* where appropriate
For boards with MAINBOARD_HAS_CHROMEOS, we should also
state what kind of storage is available for vboot's
non-volatile data.

The flags are taken from the chromium repository and
have no effect with CHROMEOS disabled.

Change-Id: I1747ad26c8c7f6d4076740ec2800dbd52c5d6b3d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9952
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-22 19:36:16 +02:00
Patrick Georgi 320ad820aa intel/broadwell: guard CHROMEOS support better
Since CHROMEOS_VBNV_* are selected by mainboards, they
may be active without CHROMEOS being selected. In this
case, they should be a no-op.

Change-Id: I3b84e2a919ffaa809d713e72e5e4df7a7575e6b9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9954
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22 19:36:08 +02:00
Aaron Durbin bd74a4b2d2 coreboot: common stage cache
Many chipsets were using a stage cache for reference code
or when using a relocatable ramstage. Provide a common
API for the chipsets to use while reducing code duplication.

Change-Id: Ia36efa169fe6bd8a3dbe07bf57a9729c7edbdd46
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8625
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-22 17:55:08 +02:00
Aaron Durbin cac5050623 coreboot: tiered imd
A tiered imd allows for both small and large allocations. The
small allocations are packed into a large region. Utilizing a
tiered imd reduces internal fragmentation within the imd.

Change-Id: I0bcd6473aacbc714844815b24d77cb5c542abdd0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8623
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-22 17:54:50 +02:00
Aaron Durbin 20686d851c coreboot: add imd library
The imd (internal memory database) library provides a way to
track memory regions by assigning ids to each region. The implementation
is a direct descendant of dynamic cbmem. The intent is to replace
the existing mechanisms which do similar things: dynamic cbmem, stage
cache, etc.

Differences between dynamic cbmem and imd:
- All structures/objects are relative to one another. There
  are no absolute pointers serialized to memory.
- Allow limiting the size of the idm. i.e. provide a maximum
  memory usage.
- Allow setting the size of the root structure which allows
  control of the number of allocations to track.

Change-Id: Id7438cff80d396a594d6a7330d09b45bb4fedf2e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8621
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-22 17:54:41 +02:00
Aaron Durbin 818e928d12 chromeos: fix some compilation issues
This fixes some compilation issues observed with CONFIG_CHROMEOS.
Nothing within the vbootX subdirectories is functional yet, but
a partial compilation within the chromeos direction works now.
Notable fixes: duplicate definitions and missing prototypes.

Change-Id: I53c7b6dcf06b8bcf41a8555094b48968c0740026
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9936
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-22 16:18:43 +02:00
Patrick Georgi b69b05d9f6 chromeos: make functions visible with CONFIG_CHROMEOS
They were keyed to VBOOT_VERIFY_FIRMWARE which made them invisible
under some circumstances.

Change-Id: I61c56b4d245351fae0ec14f80bcd17ba93184651
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9956
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-22 16:18:29 +02:00
Patrick Georgi 6e5f22eb1c elog: use CONFIG_RTC
When RTC is not selected, return all 0.

Change-Id: I892a9489fc1d82fb8e61cf02666f797dc6412e05
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9955
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-22 16:18:19 +02:00
Patrick Georgi 0770f25899 rtc: add config flag to denote rtc API availability
RTC drivers now select RTC, so that code which depends on them
can implement fallback behavior for systems that lack the
hardware or driver.

Change-Id: I0f5a15d643b0c45c511f1151a98e071b4155fb5a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9953
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-22 16:18:13 +02:00
Patrick Georgi b7fad898af chromeos: Drop {developer,recovery}_mode_enabled
They were already moved to src/lib/bootmode.c in
commit 5687fc9 Declare recovery and developer modes outside ChromeOS

Change-Id: Ia27a0c79baa364ce3779a8a699e9246d26d02ecb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9951
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-22 16:17:47 +02:00
Patrick Georgi 21edc976cc nvidia/tegra132: Add spi_crop_chunk()
Missed during upstreaming

Change-Id: Ifef4bb8a097a71244bdb648840cd64a812673107
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9950
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-22 16:17:39 +02:00
Patrick Georgi a1e514d56f google/*: Add MAINBOARD_HAS_CHROMEOS where appropriate
Some recently upstreamed boards are missing this flag

Change-Id: I89d73970f23eed6ea127e620c38f9687b2f5b048
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9949
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-04-22 16:16:08 +02:00
Patrick Georgi c082806fce vboot2: CFLAGS_* doesn't contain preprocessor flags anymore
The preprocessor flags that are manipulated in that line are
managed exclusively in CPPFLAGS since commit 58f73a69.

Change-Id: I2263401a292b4f7435659b24cf4f695a927015ef
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9948
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-22 16:15:58 +02:00
Aaron Durbin 696689bfb1 qemu-armv7: fix cbfs media implementation
When using qemu-armv7 to load coreboot.rom with the -kernel
flag the rom is offset by 0x10000. Therefore only allow
mappings within 0x10000 and 0x10000 + CONFIG_ROM_SIZE.

TEST= QEMU_AUDIO_DRV=none qemu-system-arm -M vexpress-a9 \
	-m 1024M -nographic \
	-kernel coreboot-builds/emulation_qemu-armv7/coreboot.rom

Change-Id: Ifec5761a7d54685f664c54efaa31949b8cc94bad
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9935
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-22 15:48:11 +02:00
Aaron Durbin 69cb2c2b5e coreboot: add a place to choose romstage loader
Instead of always loading romstage from cbfs provide a
way, similar to ramstage and payload, for other
program loaders to intervene. For now, only the cbfs
loader is consulted.

TEST=Booted to end of ramstage on qemu-armv7

Change-Id: I87c3e2e566d7a0723e775aa427de58af745ecdd5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9934
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-04-22 15:38:30 +02:00
Patrick Georgi 13d45aa928 kontron/986lcd-m: update vendor URL
Change-Id: Ia43291d0d41e565f2442b625387f3ffde9a98d32
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/9947
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-04-22 13:38:46 +02:00
Patrick Georgi 351bbdc37c kontron/986lcd-m: Add release year
Change-Id: Ie49e235b81ca0cd7aff05ceed522d9df1d5403b0
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/9946
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-04-22 13:38:42 +02:00
Vadim Bendebury c83687d520 vboot: route all resets through a single function
It is necessary to trigger console buffer contents dump on reset.
Let's make sure all vboot resets are routed through the same function.

BRANCH=none
BUG=chromium:475347
TEST=built and booted storm

Change-Id: I0d8580fb65417ba4b06dfae763dd6455afc8fc26
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9788e2043cb1bd5df7e30574f7df4de4f25caa0d
Original-Change-Id: Iafca416700c51a0546249438ca583a415a1ca944
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/265292
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9931
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22 09:04:00 +02:00
Icarus Chau be47636de0 broadcom/cygnus: Enable DDR auto self-refresh
Enable auto entry and auto exit self-refresh.
Configure entry idle time to 16x long count sequences.
Where a long count sequence is 1024 cycles.
The idle entry configuration is based on 32x of the DLL lock time (512 cycles).
A conservative setting to help minimize self-refresh enter/exit thrashing.

BUG=chrome-os-partner:36456
BRANCH=broadcom-firmware
TEST=When enable configuration CYGNUS_SDRAM_TEST_DDR,
print on console:

sdram initialization is completed.
test ddr start from 0x60000000 to 0x80000000
...
test ddr end: fail=0
Translation table is @ 02004000
Mapping address range [0x00000000:0x00000000) as uncached

Change-Id: Ibad220429fd52ead2933db03bec1a555f9385e53
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3768f82ca268fb854f8c4753916518a1efdf887d
Original-Reviewed-on: https://chrome-internal-review.googlesource.com/212125
Original-Reviewed-by: Scott Branden <sbranden@broadcom.com>
Original-Reviewed-by: Daisuke Nojiri <dnojiri@google.com>
Original-Commit-Queue: Daisuke Nojiri <dnojiri@google.com>
Original-Tested-by: Daisuke Nojiri <dnojiri@google.com>
Original-Signed-off-by: Icarus Chau <ichau@broadcom.com>
Original-Change-Id: Icac1e12745d048b32e1804a546f6b49c8b5953c0
Original-Reviewed-on: https://chromium-review.googlesource.com/265862
Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Original-Trybot-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: http://review.coreboot.org/9930
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22 09:03:46 +02:00
Corneliu Doban bcdbdc6761 broadcom/cygnus: add specific controller initialization to coreboot
BUG=chrome-os-partner:37533,chrome-os-partner:35814
BRANCH=broadcom-firmware
TEST=bootblock initialize Cygnus HW successfully

Change-Id: I93b97d7b26f6bacd8fab3d6bc52ec52e92e91a43
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8679570c6607ed6964f46df618fe8d0d22fcb2c0
Original-Reviewed-on: https://chrome-internal-review.googlesource.com/211695
Original-Tested-by: Corneliu Doban <cdoban@broadcom.com>
Original-Reviewed-by: Daisuke Nojiri <dnojiri@google.com>
Original-Reviewed-by: Scott Branden <sbranden@broadcom.com>
Original-Commit-Queue: Corneliu Doban <cdoban@broadcom.com>
Original-Signed-off-by: Corneliu Doban <cdoban@broadcom.com>
Original-Change-Id: I62d354bce71aba8d5074f5385616a1265bd604df
Original-Reviewed-on: https://chromium-review.googlesource.com/265861
Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Original-Trybot-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: http://review.coreboot.org/9929
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22 09:03:29 +02:00
Jonathan Dixon 2580508a11 google/veyron_rialto: support the developer key GPIO
Currently (EVT) this is a pullup resistor on the board (i.e. always in
dev mode). Future builds it will be pull down and require servo or HW
modification to control. Either way, this change means the FW should
acknowledge it.

BUG=chrome-os-partner:38663
TEST=Manually verified that servo devmode switch toggles this GPIO. requires FW signing to verify GPIO is observed and dev mode active.
BRANCH=none

Change-Id: Ib05216992abc5f6175fe7395471bd379f185b61f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 702c8d222a3d19d6b8db89d122dcdf594c85da99
Original-Change-Id: I1d0f31819b9f7a1ab63deac52bcaf0b996499b0c
Original-Reviewed-on: https://chromium-review.googlesource.com/263529
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Original-Tested-by: Jonathan Dixon <joth@chromium.org>
Original-Commit-Queue: Jonathan Dixon <joth@chromium.org>
Reviewed-on: http://review.coreboot.org/9928
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22 09:03:10 +02:00