Fixed write_page_write_jedec() in jedec.c. Added a check-reprogram loop
in the same function, to come around the high page write failure rate on
some boards.
This patch includes the changes suggested by Ron to simplify the control
flow.
It also includes trivial changes by me to make flashrom build on newer
systems (libpci needs libz now). I also made a small type case compile fix
and proper return code handling in one or two places.
Signed-off-by: Giampiero Giancipoli <gianci@email.it>
Signed-off-by: Ronald G Minnich <rminnich@gmail.com>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2505 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
flash chips to flashrom (closes: #50).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2501 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
will detect any improper erase, closes#31
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2494 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Add detailed instructions on how and where to get the datasheet,
its name, and order number (Closes#34).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2493 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Tested on real hardware, reading, detecting and writing various chips works.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2489 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
by Uwe Hermann <uwe@hermann-uwe.de>
X-Signed-Off-By: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2450 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
from Uwe Hermann <uwe@hermann-uwe.de>
X-Signed-Off-By: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2449 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
by Roman Kononov <kononov195-lbl@yahoo.com>.
X-Signed-Off-By: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2448 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* https://openbios.org/roundup/linuxbios/issue99 - add ICH4-M support to flashrom
both from scott.tsai <AT> arima.com.tw
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2230 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Support for ATI SB400 (RS480 chipset)
* Support for Intel ICH7 (from Scott Tsai, scott.tsai <AT> arima.com.tw)
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2229 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- support for flashing technologic system ts5300 SBC (needs -DTS5300 in
the makefile)
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2205 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
other fixes for gx2 ram init.
support for sharplfg00l04 -- not working yet.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2197 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* do case insensitive comparison of mainboards, as wished on the
mailinglist
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2146 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Giampiero Giancipoli