Commit Graph

39170 Commits

Author SHA1 Message Date
Furquan Shaikh 4a1cbdd51a soc/intel/common/cse: Perform cse_fw_sync on BS_PRE_DEVICE entry
This change drops the special check added for TGL/JSL platforms and
performs cse_fw_sync on BS_PRE_DEVICE entry. This was being done later
in the boot process to ensure that the memory training parameters are
written back to SPI flash before performing a reset for CSE RW
jump. With the recent changes in CB:44196 ("mrc_cache: Update
mrc_cache data in romstage"), MRC cache is updated right away in
romstage. So, CSE RW jump can be performed in BS_PRE_DEVICE phase.

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I947a40cd9776342d2067c9d5a366358917466d58
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
2020-12-02 21:53:17 +00:00
Felix Held a5a529599d soc/amd: factor out common SMI/SCI enums and function prototypes
At least a part or the remaining definitions in the soc-specific smi.h
files are also common, but those have to be verified more closely.

Change-Id: I5a3858e793331a8d2ec262371fa22abac044fd4a
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-02 21:33:14 +00:00
Felix Held f42da176de soc/amd/common/smbus: remove misleading definition
SMBHST_STAT_NOERROR was a redefinition of SMBHST_STAT_INTERRUPT that was
used in smbus_wait_until_done. Remove the misleading bit definition that
also didn't correspond with the register definitions and replace it with
the definition of the actual bit that gets checked. Also add a comment
that the code actually checks the IRQ status flag to see if the last
command is already completed.

Change-Id: I1a58fe0d58d3887dd2e83320e977a57e271685b3
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48219
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-02 21:28:19 +00:00
Felix Held 43a5f88bb4 soc/amd: factor out fch_smbus_init
Change-Id: I6df9323dc4e7ca99fd5368f0262e850c0aca5c54
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-02 21:27:49 +00:00
Felix Held 875e5aa96c soc/amd: factor out SMBUS controller registers into common header
The patch also rewrites the bit definition using shifts to make them
easier to read.

The older non-SoC chips can probably also use the new header file, but
for this patch the scope is limited to soc/amd, since the older non-SoC
chips don't use the SMBUS controller code in soc/amd/common.

TEST=Timeless build for amd/mandolin and amd/gardenia doesn't change.

Change-Id: Ifd5e7e64a41f1cb20cdc4d6ad1e675d7f2de352b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-02 21:27:21 +00:00
Felix Held 6443ad4a53 soc/amd: factor out common AOAC device enable and status query functions
The code on Stoneyridge didn't set the FCH_AOAC_TARGET_DEVICE_STATE bits
to FCH_AOAC_D0_INITIALIZED like the code for Picasso does, but that is
the default value after reset for those bits on both platforms.

Change-Id: I7cae23257ae54da73b713fe88aca5edfa4656754
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-02 21:27:03 +00:00
Felix Held 5b3831c75a soc/amd: factor out common AOAC definitions
The register locations and bit definitions are the same for Stoneyridge
and Picasso. Since not all devices are present on all SoCs, keep those
numbers in the SoC-specific code.

Change-Id: Ib882927e399031c376738e5a35793b3d7654b9cf
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-02 21:26:50 +00:00
Mike Banon f7b410d409 vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support a custom memory profile
The ability to set up a custom memory profile is useful if you don't
like the XMP memory profiles (if they exist) of your RAM sticks, or
want to try some overclocking. Read SPD data will be overriden by your
custom values. Tested on Crucial BLT8G3D1869DT1TX0 (1866MHz 9-9-9-27).

Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I1238ff00ef0efd11ea807794827476c30ac98065
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-12-02 18:18:27 +00:00
Mike Banon 3ee9935f63 vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles
Add XMP memory profiles support that has been tested on f15tn (A88XM-E)
and f16kb (AM1I-A) with two Crucial BLT8G3D1869DT1TX0, XMP 1 profile.
Added using the datasheets from https://github.com/mikebdp2/ddr3spd :
JEDEC_DDR3_SPD_4_01_02_11R24.pdf and Intel_XMP_Spec_Rev1.1.pdf

Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I584416e3376afdf377a11783e55c5e9ff41e6b0d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40488
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-02 17:05:39 +00:00
Patrick Rudolph 03a339126b soc/intel/skylake: Fix compilation under x86_64
Change-Id: I37382ab06a8f1760e955d1ec76a6a00958b05999
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48177
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-02 16:49:12 +00:00
Patrick Rudolph 484adee53e cpu/x86/smm/smm_stub: Fix stack canary on x86_64
On x86_64 the cannary is 8 bytes in size, so write the additional
4 bytes to make SMM handler happy.

Tested on Intel Skylake in long mode. No longer dies in SMM.

Change-Id: Id805c65717ec22f413803c21928d070602522b2c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48215
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-02 16:48:35 +00:00
Patrick Rudolph 9e7497e64f cpu/x86/smm/smm_stub: Fix GDT for x86_64
The previous code was crashing when jumping back to ramstage, now it
works. The GDT is now using the same values as the other ones in
coreboot.

Change-Id: Id00467d9d8a4138ddea73adbda4b39f12def583f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48214
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-02 16:48:25 +00:00
Duncan Laurie 89bbe146cb mb/google/volteer: Add fw_config entries for boot device
Add the fw_config entries for the newly added boot device fields.
These are added as separate fields since a board may have more
than one selected.

BUG=b:173129299
TEST=abuild google/volteer

Change-Id: I2af9ffcf0b90d4f4b7f2f31613ee110d8f350454
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-02 16:31:44 +00:00
Duncan Laurie 912d9ec158 mb/google/volteer: Add additional SD cards to device list
The initial commit only focused on GL9755S and RTS5261, but there
were recently other cards added to the fw_config and those also
need to be added to the probe lists.

BUG=b:173207454
TEST=abuild google/volteer

Change-Id: Ic27074a016ffbd4c4dd86104a6d85437357c4b82
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-02 16:31:33 +00:00
Felix Held 3cc3d818e8 soc/amd/picasso: add FSP binary location
Now that the initial version of the Picasso FSP binaries have finally
landed, we can set the default paths to point to them now.

Change-Id: Ib2241cc90c7113e0c3de4409e08b9ae1f4c2f51e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42472
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-02 15:21:09 +00:00
Marshall Dawson 535fa0a1cd 3rdparty/amd_blobs: Update pointer for picasso SMU and FSP
Add the newest SMU firmware and FSP blobs for the picasso project.
This supports Picasso, Dali, and Pollock devices.

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I75e6f3d2a59ed8b2e42afba3a6978574373ec4e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-02 15:20:35 +00:00
Meera Ravindranath 56ccbf3b60 mb/intel/adlrvp: Replace tab by white space in devicetree
Change-Id: I928b4528fa5b4c378a2e8ff7bb88547da1413df2
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48213
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-02 15:08:47 +00:00
Tan, Lean Sheng e8e6d8610c vendorcode/intel/fsp: Add Elkhart Lake FSP headers for FSP v2341
The FSP-M/S/T related headers added are generated as per FSP v2341.

Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I98f738402490b47efa1a346f81db47857e384e13
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-12-02 10:44:57 +00:00
Tan, Lean Sheng ece0fe3f23 soc/intel/elkhartlake: Update Kconfig
Update Kconfig:
1. use FSP2.1 instead of 2.2
2. remove HECI_DISABLE_USING_SMM config
3. update CAR related stack & ram size
4. update FSP heap size
5. set IED region size = 0 as it is not used
6. update SMM TSEG size
7. update RP & I2C max device #s
8. update UART base address

Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I6a44d357d71be706f402a6b2a4f2d4e7c0eeb4a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45078
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-02 10:44:48 +00:00
Paul Menzel 270a32370d soc/intel/skylake: Map VBIOS IDs
The extracted VBIOS Option ROM ships the same ID for several
generations, not matching the ID on the hardware resulting in a
mismatch, and coreboot does not run the Option ROM.

    PCI ROM image, vendor ID 8086, device ID 0406,
    ID mismatch: vendor ID 8086, device ID 5916

Add the appropriate mappings.

TEST=coreboot runs the ROM on the TUXEDO Book BU1406.

Change-Id: Ia167d91627a7ff1b329ea75f150b3ce95c0acccb
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43853
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-02 10:43:50 +00:00
Karthikeyan Ramasubramanian 1f45104d1a mb/google/dedede/var/drawcia: Support VBT for Drawman
Default VBT supports only integrated Display port. Drawman supports a
HDMI port and hence support a separate VBT for Drawman.

BUG=b:161190931
BRANCH=dedede
TEST=Build and boot to OS in Drawlat and Drawman.

Cq-Depend: TBD
Change-Id: I8895cc67d87428eddb31328f1e3a90c346b54533
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2020-12-02 10:42:52 +00:00
Karthikeyan Ramasubramanian 291fd9fec9 mb/google/dedede: Add Daughter-board FW_CONFIG in devicetree
Add daughter-board ports bit field and mask in devicetree.

BUG=b:161190931
BRANCH=dedede
TEST=Build and boot to OS in drawlat & drawman.

Change-Id: Ibbd86fc8c3e44a7d1703b8ce75c48881226545c9
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2020-12-02 10:42:41 +00:00
Ronak Kanabar e0268a4477 vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2385_04
The headers added are generated as per FSP v2385_04.
Previous FSP version was 2385_02.
Changes Include:
- add FastPkgCRampDisable, SlowSlewRate, PreWake, RampUp and
RampDown UPDs in Fsps.h

BUG=b:174330941
BRANCH=dedede
TEST=Build and boot JSLRVP

Cq-Depend: chrome-internal:3438485
Change-Id: I477af05c34f767a43990670a711992641eaf6000
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47862
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-02 10:42:28 +00:00
Kane Chen 431f8cb08a mb/google/zork: Update SPD table for Shuboz
Add memory table to "mem_parts_used.txt", and command to generate files:
go build gen_part_id.go
./gen_part_id ../../../src/mainboard/google/zork/spd
../../../src/mainboard/google/zork/variants/shuboz/spd/
../../../src/mainboard/google/zork/variants/shuboz/spd/mem_parts_used.txt

Shuboz memory table as follow:
value	Vendor	Part number
0x00	MICRON	MT40A512M16TB-062E:J
0x01	HYNIX	H5AN8G6NCJR-XNC
0x02	MICRON	MT40A1G16KD-062E:E
0x03	SAMSUNG	K4AAG165WA-BCWE

BUG=b:174528384
BRANCH=zork
TEST=emerge-zork coreboot

Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I5f5f875daab58343f1cc8a9327ea128ba5e1f050
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2020-12-02 10:41:55 +00:00
Tony Huang bb70099083 mb/google/dedede/var/lantis: Configure IRQs as level triggered for HID over I2C
Config HID-I2C device to level trigger.
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4,
the interrupt line used by the device is required to be level triggered.
Hence, this change updates the configuration of the HID over I2C devices
to be level triggered.

References:
[1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx

BUG=b:171546871
TEST=emerge-dedede coreboot

Change-Id: If8be25f591715765a99920b79482c862b1cc7079
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-02 10:41:46 +00:00
Arthur Heymans c27628e2b7 arch/x86/car.ld: Check for out of bound on no-XIP stages
Check that stages running in CAR have their start and end in CAR.

Change-Id: I292aacce564c23d9ae21aa46c5e2f8784fa6a609
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-12-02 10:41:00 +00:00
Daniel Gröber 2aa15872d2 edist-test: Fix _Static_assert missing message string
Older GCCs don't support _Static_assert without a message string as the
second argument. AFAICT _Static_assert with two arguments is in C11 but
omitting the message argument is an extension.

The tests appear to be built with the system gcc rather than our
crossgcc so that's probably why this was not cought by CI.

Change-Id: I41fd0ffc42ded8b6d145c3ec30cc7407a78b9a43
Signed-off-by: Daniel Gröber <dxld@darkboxed.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-12-02 10:38:25 +00:00
Ronak Kanabar 7c0f007cf5 src/acpi/acpigen: Add NULL pointer check
Add NULL pointer check in acpigen_emit_namestring
to avoid segmentation fault.

Change-Id: I3d01d28e74f202278b5a5a96d2edd45c66f10883
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48148
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-02 06:07:05 +00:00
Felix Held ab0d85c987 soc/amd/stoneyridge: align AOAC code with Picasso
In commit 09d50671e6 the AOAC code was
reworked for Picasso and this patch ports this back to Stoneyridge to
facilitate factoring out the functionality into common code.

Change-Id: I836b91dc647987d064170fff7c8ca6ef2ee49211
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-01 20:59:32 +00:00
Felix Held 0d57f42e83 soc/amd/picasso/aoac: make aoac_devs array unsigned
The numbers in the array are unsigned, so use an unsigned type there.

Change-Id: I9a85594de0e4c53db965ab84239f19eb46432348
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-01 20:59:19 +00:00
Felix Held 9bc16ed856 soc/amd/picasso/aoac: fix typo in comment
The power_off_aoac_device function clears the FCH_AOAC_PWR_ON_DEV bit,
so the comment should be that it powers off the devices.

Change-Id: Ia5e5d80b1977c3f53fcd9cf6d48bdb59045dfc3c
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48155
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-01 18:07:33 +00:00
Patrick Rudolph ee38ccecf8 soc/intel/common/block/smm/smihandler: Fix compilation under x86_64
Change-Id: Ie44ded11a6a9ddd2a1163d2f57dad6935e1ea167
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-01 16:02:19 +00:00
Patrick Rudolph ed5835a04d soc/intel/common/block/cpu/car/exit_car: Fix compilation on x86_64
Change-Id: Ieac4a4924ff4684b2a419471cd54e3d3b1f5bbe6
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48171
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-01 16:01:58 +00:00
Patrick Rudolph 2b77112e66 soc/intel/common/block/cpu/car/cache_as_ram: Add x86_64 support
Doesn't affect x86_32.
Tested on Intel Skylake. Boots into bootblock and console is working.

Change-Id: I1b36ca8816dab9d30754aadd230c136978e3b344
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48170
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-01 16:01:44 +00:00
Patrick Rudolph 0e3884cfff drivers/aspeed/common/ast: Fix compilation under x86_64
Change-Id: I5fb6594ff83904df02083bcbea14b2d0b89cd9dd
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-01 16:01:31 +00:00
Patrick Rudolph 90fda02f60 drivers/intel/fsp2_0/notify: Fix compilation under x86_64
Change-Id: Id63b9b372bf23e80e25b7dbef09d1b8bfa9be069
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-01 16:01:19 +00:00
Patrick Rudolph 3805354ff9 soc/intel/common/block/systemagent: Fix compilation on x86_64
Change-Id: Ibc8dc1cf33f594284edb82d4730967e077739c3c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-01 16:01:10 +00:00
Patrick Rudolph 2dbbb83ae4 lib/reg_script: Add cast to fix compilation on x86_64
Change-Id: Ia713e7dbe8c75b764f7a4ef1a029e64fb2d321fb
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-01 16:00:57 +00:00
Patrick Rudolph 429c77a5e3 cpu/x86/early_reset: Mark assemblycode as 32bit
Allows to compile the file under x86_64 without errors.

The caller has to make sure to call the functions while in protected
mode, which is usually the case in early bootblock.

Change-Id: Ic6601e2af57e0acc6474fc3a4297e3d2281decd6
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-01 16:00:40 +00:00
Patrick Rudolph 983ea18f17 cpu/intel/microcode: Mark assemblycode as 32bit
Allows to compile the file under x86_64 without errors.

The caller has to make sure to call the functions while in protected
mode, which is usually the case in early bootblock.

Change-Id: Ic6d98febb357226183c293c11ba7961f27fac40c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-01 16:00:34 +00:00
V Sowmya a99f61fec4 mb/intel/jslrvp: Modify the flash layout for fsp debug build
Current flash layout doesn't support the fsp debug builds since
the FW_MAIN_A/B doesn't have enough space to hold the fsp debug
binaries along with ME RW binaries.
This patch reduces the SI_ALL size to 3.5MiB and increase the
SI_BIOS to 12.5MiB to include both ME RW and FSP debug binaries.

BRANCH=dedede
TEST=Build and Boot jslrvp with fsp debug enabled coreboot.

Cq-Depend: chrome-internal:3425366
Change-Id: I6f6354b0c80791f626c09dabafe33eefccedb9c2
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48154
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-12-01 15:27:01 +00:00
Martin Roth e2ce56928c mb/google/zork: Mark RW_MRC_CACHE as "Preserve"
AGESA checks to make sure that the firmware version reading the MRC
cache is the same version that wrote it, so it doesn't need to be
erased during a firmware update.

BUG=b:173724014
TEST=Flash firmware to DUT, update firmware, check RW_MRC_CACHE was
not erased
BRANCH=Zork

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ice3d1d467c25366b7ef678cd6481d043f62644ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47776
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-01 15:24:13 +00:00
Patrick Rudolph a169550479 cpu/x86/sipi: Add x86_64 support
Enter long mode on secondary APs.

Tested on Lenovo T410 with additional x86_64 patches.
Tested on HP Z220 with additional x86_64 patches.

Still boots on x86_32.

Change-Id: I53eae082123d1a12cfa97ead1d87d84db4a334c0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-01 14:53:44 +00:00
Felix Singer 45dc92a8c2 mb/kontron/mal10: Use the system library for headers
Use the system library for header files instead of relative filesystem
paths.

Built with BUILD_TIMELESS=1, coreboot.rom remains the same.

Signed-off-by: Felix Singer <felixsinger@posteo.net>
Change-Id: I0b356d0188f104d7c49571ce5c8fe65e79589123
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-12-01 13:47:39 +00:00
Felix Singer fee6974452 mb/kontron/mal10/Kconfig: Reorder selects alphabetically
Built with BUILD_TIMELESS=1, coreboot.rom remains the same.

Signed-off-by: Felix Singer <felixsinger@posteo.net>
Change-Id: Id78c478a1252099cd1aa42c62efd406e7e1c5ef8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48140
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-12-01 13:47:20 +00:00
Felix Singer 3c02ed9cb6 MAINTAINERS: Add missing trailing slashes
Add missing trailing slashes so that Gerrit recognizes maintainers
correctly.

Signed-off-by: Felix Singer <felixsinger@posteo.net>
Change-Id: I35fcaf41617247e2b86cd6ddd7ee1b319a695797
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48137
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-01 13:46:54 +00:00
Tim Chu 39ea223249 mb/ocp/deltalake: Update SMBIOS type 8 information
Update port connector information for Delta Lake.

Tested=Execute "dmidecode -t 8" to check all the information of
SMBIOS type 8 is correct.

Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I880bb9a5a41077172423f78b56c19aadd93e001f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-01 08:04:30 +00:00
Subrata Banik f5c3e29bdf ec/google/chromeec/acpi: Make OperationRegion brace align
Inject TAB to make OperationRegion closing brace align with
opening brace.

Change-Id: Idb9f23cf6a2c249fb1fd02f4a2ac314d4f7e180b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-01 08:00:23 +00:00
Subrata Banik 52fabb1247 mb/intel/adlrvp: Remove unused EC_SYNC_IRQ GPIO on ADLRVP
As per latest schematics GPP_A15 is not used for EC_SYNC_IRQ
hence remove the unused GPIO.

Wrong GPIO configuration is causing platform reboot issue on
ADLRVP with Chrome SKU.

Change-Id: I704cd722683258c80197d8872d3bdaafb7c923dc
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
2020-12-01 08:00:09 +00:00
Varshit Pandya 5e1d4dd947 mb/intel/adlrvp: Add ASL support for WFC annd UFC
1. Add 2 ports and 2 endpoints
2. Add support for OVTI5675

WFC Cam is on I2C5 and UFC is on I2C1
BUG=None
BRANCH=None
TEST=Build and Boot adlrvp board and able to capture image
using camera.

Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com>
Change-Id: I6d2a4fdca99354d1b6977233c70ccd950c99d8a2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47497
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-01 07:59:52 +00:00