Commit graph

6 commits

Author SHA1 Message Date
Paul Menzel
a46a712610 GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«
In the file `COPYING` in the coreboot repository and upstream [1]
just one space is used.

The following command was used to convert all files.

    $ git grep -l 'MA  02' | xargs sed -i 's/MA  02/MA 02/'

[1] http://www.gnu.org/licenses/gpl-2.0.txt

Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2490
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-03-01 10:16:08 +01:00
Ronald G. Minnich
5079a0d32f Remove assembly coded log2 function
As we move to supporting other systems we need to get rid of assembly
where we can. The log2 function in src/lib is identical to the assembly
one (tested for all 32-bit signed integers :-) and takes about 10 ns
to run as opposed to 5ns for the non-portable assembly version. While speed
is good, I think we can spare the 15 ns or so we add to boot time
by using the C version only.

Change-Id: Icafa565eae282c85fa5fc01b3bd1f110cd9aaa91
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/1928
Tested-by: build bot (Jenkins)
2012-11-28 07:57:17 +01:00
zbao
366f0fc30a AMD SB: Call the rtc update if needed (Propagation)
Apply the change
http://review.coreboot.org/1390
to all the AMD southbridge.

Change-Id: I8e94014f8883a0408b68355d9aa33aea4373881f
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1406
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2012-08-05 07:01:26 +02:00
Patrick Georgi
2c2e78d845 Unify IO APIC address specification
Some places still hardcoded the address instead of using IO_APIC_ADDR.

Change-Id: I3941c1ff62972ce56a5bc466eab7134f901773d3
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/677
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-04-12 00:06:11 +02:00
Rudolf Marek
74ad66cdc1 Attached patch fixes the LPC decode ranges of SB600/SB800. We enable early only Serial/SIO/RTC.
Everything else needs to be done by lpc.c Problem was that early settings survived, because the lpc.c is doing ORs only...
Hence we decode quite a lot and even strange ranges like IO port 0x4600 etc...

Also, if some port which does not fit to predefined set is requested, like 0x290 for Hardware monitor, the wide port is done, but in our case it has range 512 bytes which means we decode in fact 0x290 - 0x490. And if we hit GPU in the 0x3bx range I receive MCE exception if I do isadump -f 0x300 which is bad.
Therefore If I detect that the requested range is small (16 bytes) I additionally set the small wide io region so only 16 bytes is decoded.

While at it, I fix spelling typos and I init the regs so we don't write random garbage to regs even if we don't enable them later.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz> 
Acked-by: Marc Jones <marcj303@gmail.com>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6343 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-12 16:24:48 +00:00
Zheng Bao
d098575b0e This sb800 code is derived from sb700.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6277 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-20 04:45:48 +00:00