Commit Graph

2538 Commits

Author SHA1 Message Date
Uwe Hermann 969a9f69e8 Various smaller fixes in superiotool:
- Also dump the extra registers (e.g. EC regs) in --list-supported.

 - Small fix in the code to allow for building with -pedantic (yes,
   the fix is a bit silly, but it's simple and allows us to use the
   -pedantic flag to keep the code even cleaner and nicer).

 - Install the binary in /usr/sbin, as it's meant to be run as root.

 - Small typo in README.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3163 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-17 13:43:48 +00:00
Uwe Hermann a2ccf9fe4e Add support for the MSI MS-6119 mainboard.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3162 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-17 13:37:34 +00:00
Carl-Daniel Hailfinger fa510c7878 Clarify LZMA code license.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3161 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-17 01:37:27 +00:00
Ed Swierk 4f83d7ed96 oops. sorry, wrong checkin. This patch backs out r3155 and instead contains the
code it should have contained.

This patch updates the PCI IDs for Intel 3100 devices.

Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3160 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-16 23:43:04 +00:00
Ed Swierk 354e2d3dc1 This patch implements support for the Intel 3100 Development Kit
mainboard, aka "Mt. Arvon".   

Signed-off-by: Ed Swierk <eswierk@arastra.com>                                                                                                                                               
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3159 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-16 23:39:24 +00:00
Ed Swierk a9faea8977 This patch implements support for the Intel 3100 integrated
northbridge and RAM controller. 

Signed-off-by: Ed Swierk <eswierk@arastra.com>                                                                                                                                               
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3158 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-16 23:36:00 +00:00
Ed Swierk aaea11b749 Here is an updated patch addressing most of Uwe's and Peter's
comments. Ripping out the ehci/uhci_init() code doesn't seem to have                                                                                                                         
done any harm, and I got rid of a bunch of unused junk in                                                                                                                                    
i3100_smbus.h                                                                                                                                                                                
                                                                                                                                                                                             
I left the *_set_subsystem() arguments unsigned, as that's how the                                                                                                                           
function is declared in include/device/pci.h.                                                                                                                                                
                                                                                                                                                                                             
Signed-off-by: Ed Swierk <eswierk@arastra.com>   
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3157 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-16 23:34:10 +00:00
Ed Swierk 62eee3ff4f This patch implements support for the Intel 3100 integrated SuperIO and UART.
Signed-off-by: Ed Swierk <eswierk@arastra.com>                                                                                                                                               
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>                                                                                                                                                   
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3156 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-16 23:31:04 +00:00
Ed Swierk 791265a367 This patch updates the PCI IDs for Intel 3100 devices.
Signed-off-by: Ed Swierk <eswierk@arastra.com>                                                                                                                                               
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>                                                                                                                                                   
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3155 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-16 23:27:50 +00:00
Stefan Reinauer a4b901e3ef give the fam10 code a little more space until we have the time to debug this
properly. Everybody knows this by now.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3154 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-16 22:20:53 +00:00
Stefan Reinauer dd6877a46d check whether SST FWH chip was successfully erased on flashchip -E, too
(trivial)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3153 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-16 19:44:13 +00:00
Uwe Hermann 568667da20 Sort list of flash chips alphabetically, add comment (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3152 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-16 02:06:25 +00:00
Stefan Reinauer 582ce71cc5 remove nasty warning that happened due to our vendor detection
mechanism.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3151 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-15 23:41:19 +00:00
Stefan Reinauer 9dcfc00dc6 fix typo
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3150 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-15 16:30:39 +00:00
Stefan Reinauer e989be26e6 BIOS_SPEW is log level 9. There is nothing beyound that line.
(Thus the patch is trivial)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3149 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-15 12:26:12 +00:00
Rudolf Marek 5671787b9e Following patch extends the ROM decoding to last 1MB, allowing to use larger
flashes such as SST49LF080A: 1024K x8 (8 Mbit)

Tested on my system, the flash is found and if I use coreboot in second half it
works too.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3148 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-15 00:26:50 +00:00
Rudolf Marek dd52e17448 Following patch fixes the retrain/reset sequence which caused problem with some
nVidia cards. The enable link should be enough, retrain is done there.

Tested on my system.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3147 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-15 00:19:34 +00:00
Uwe Hermann 1ce63770a1 Re-add code erroneously removed in r3140.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3146 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-14 23:55:58 +00:00
Joseph Smith 937ae9d9fe Changes M50FW080 to use 82802ab.c instead of jedec.c. This fixes the problem of not being able to erase the chip.
Signed-off-by: Joseph Smith <joe@smittys.pointclark.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3145 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-14 23:32:03 +00:00
Carl-Daniel Hailfinger ae8a08df3b Prepare for ICH7/ICH8 SPI support by adding some debugging for all
ICH* chipsets. Functionality (except printing) should be unchanged.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Ward says:
This code detects the ICH8 chipset on my laptop, and it appears to use
SPI.

Acked-by: Ward Vandewege <ward@gnu.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3144 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-14 17:20:59 +00:00
Corey Osgood 0b202d0a6e Add a Config-abuild.lb for the rca/rm4100 (trivial)
The problem is explained here: http://www.coreboot.org/pipermail/coreboot/2008-March/032185.html

Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3143 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-14 06:12:24 +00:00
Uwe Hermann c843636c88 Fix broken flashrom build.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3142 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-14 01:24:39 +00:00
Carl-Daniel Hailfinger 4b0a41b5ca Fix up one forgotten revert in r3140.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3141 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-14 00:33:42 +00:00
Carl-Daniel Hailfinger 8729de48fa Revert the delete of 82802ab.c in r3137.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3140 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-14 00:02:25 +00:00
Uwe Hermann 912ee57a59 Also print the chip vendor name in --list-supported output (trivial).
Cosmetic changes in some files, partly bending the 80-characters-per-line
rule in this special case, as the 80-character-limited version looks
equally crappy even in an 80x25 console/xterm, so let's make it at least
look good in a high-resolution xterm.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3139 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-13 18:52:51 +00:00
Uwe Hermann ee2bb3a21e Also print the required -m option in --list-supported output (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3138 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-13 18:41:07 +00:00
Carl-Daniel Hailfinger b7b22e3c57 Drop 82802ab.c as it is identical to sharplhf00l04.c.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3137 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-13 12:43:31 +00:00
Uwe Hermann 3182122c3b Update AMD CPU list based on Revision Guide for AMD NPT Family 0Fh Processors,
Publication #33610, Revision: 3.30, February 2008.

http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3136 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-13 02:21:41 +00:00
Uwe Hermann b681570e7b Formatting fixes, no content changes (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3135 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-12 23:18:04 +00:00
Uwe Hermann 2ad17532a4 Drop the useless rom.layout file. It's just an example, likely never
been used in the last few years, and the contents are available in
the README already anyway.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3134 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-12 12:28:40 +00:00
Uwe Hermann 098913dadf Add --list-supported option to flashrom which lists the supported
ROM chips, chipsets, and mainboards (Closes #90).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3133 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-12 11:54:51 +00:00
Stefan Reinauer 2aa1436777 Add GPIO dumping utility for Intel ICH series southbridges.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Signed-off-by: Joseph Smith <joe@smittys.pointclark.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3132 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-10 22:26:18 +00:00
Ward Vandewege 0719b8e460 The ATI vga rom is only 36K on the Tyan s2881.
This is a trivial patch.

Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3131 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-10 19:53:30 +00:00
Ward Vandewege 7aad44c496 This patch changes the Config.lb files and adds a Config-lab.lb file for the
tyan s2881 board, in preparation of supporting it in buildrom. Corresponding
changes for the other buildrom-supported boards were committed in r3092.

Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3130 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-10 18:48:52 +00:00
Joseph Smith 6a1dc86005 Initial support for the Intel 82830 northbridge and RCA RM4100 board.
Signed-off-by: Joseph Smith <joe@smittys.pointclark.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3129 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-09 13:24:46 +00:00
Uwe Hermann c4f5365688 Various cosmetic and coding style fixes for ASUS A8V-E SE (trivial).
No functional changes, only cosmetics. This is compile-tested.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3128 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-08 19:14:42 +00:00
Uwe Hermann 917158f803 Drop some duplicate documentation from the README. The manpage and
'superiotool --help' already provide the same information (trivial).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3127 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-04 17:21:04 +00:00
Uwe Hermann 9ae23628fb Add missing license header to layout.c. The file was written by
Stefan Reinauer for coresystems GmbH in 2005, as confirmed on IRC.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3126 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-04 16:29:54 +00:00
Uwe Hermann cbb5ba8633 Rename lxbios to nvramtool, step 3 (rename directory).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3124 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-01 19:09:01 +00:00
Uwe Hermann 66d83cfa84 Rename lxbios to nvramtool, step 2 (rename files).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3123 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-01 19:07:46 +00:00
Uwe Hermann 6e565947a5 Rename lxbios to nvramtool.
This is step 1 in a three-step commit:

 1. Apply patch, commit.

 2. Rename some files:
    $ svn mv lxbios.c nvramtool.c
    $ svn mv lxbios.1 nvramtool.c
    $ svn mv lxbios.spec nvramtool.spec
    $ svn ci

 3. Rename lxbios directory:
    $ svn mv lxbios/ nvramtool/
    $ svn ci

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3122 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-01 19:06:32 +00:00
Uwe Hermann eec5ff4ccb Small coding style fixes and documentation updates (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3121 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-01 18:49:39 +00:00
Corey Osgood a04027efca Create a genacpi directory below util/ which will hold all acpi related
code/data generation utilities.

Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3120 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-01 15:33:03 +00:00
Ronald Hoogenboom 9b6b63eac0 In pci_device.c, the class for VGA was not tested properly, leading to
no VGA output from coreboot, even after the boot-rom was executed
properly (CONFIG_PCI_ROM_RUN) or no boot-rom execution with
CONFIG_VGA_ROM_RUN at all. According to the header file device.h, the
class field of struct device is '3 bytes: (base,sub,prog-if)'.

Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl>
Acked-by: Torsten Duwe <duwe@lst.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3119 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-28 23:10:38 +00:00
Ward Vandewege 17632a205e Temporarily disable the fan control patch from this morning; it turns out to
stop the CPU fan on the m57sli v1.1 (PLCC) entirely, which is less than
desirable. I did not notice before because my board ran fine for about 15
minutes before the CPU overheated.

Thankfully the board has a good failsafe mode - it just switches off when the
CPU gets too hot, without permanent damage.

I'm debugging this and plan to commit a proper fix later in the week.

This is not really trivial, but the tree is dangerous in the current state so
I'm self-acking.

Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3118 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-26 04:36:52 +00:00
Ronald Hoogenboom 0be73bbf30 This patch adds support to dump other registers than the primary
pnp-style configuration registers, using the new option -e/--extra-dump.
This patch only adds dumping of the Environmental Controller
configuration registers for the IT8716f chip.

Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl>

I (Carl-Daniel) checked the data sheets of the whole IT87[012] series 
and although the environment controller is sometimes called fan 
controller, the location of the register is the same for all models.

Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3117 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-25 22:32:41 +00:00
Ronald Hoogenboom 56cf01f29d This patch adds automatic fan control for the CPU fan on the m57sli
board.

This is done via the ec_init routine in a source file in the
mainboard/gigabyte/m57sli directory. A Config variable 'HAVE_FANCTL' has been
added to notify superio.c to get the ec_init externally.

I (Ward) have tested this on the PLCC and the SOIC/SPI version of this board.
It works.

Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3116 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-25 19:36:20 +00:00
Ronald Hoogenboom 8684520b94 This trivial patch removes an unused local variable, thus getting rid of
a compiler warning.

Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3115 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-25 10:15:10 +00:00
Ward Vandewege 0be722c508 The proprietary VGA rom is only 36K on Tyan s2882, not 48K.
Tested on real hardware.

This is a trivial patch.

Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3114 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-21 21:00:19 +00:00
Corey Osgood bd3f93e330 Add support for the Via CN700 with a C7 CPU and DDR2 RAM. Only a single DIMM is
working for now, and more work is needed for it to be fully dynamic. However,
just about any 128MB-512MB DIMM should work.

Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3113 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-21 00:56:14 +00:00