Commit Graph

11869 Commits

Author SHA1 Message Date
Edward O'Callaghan a9a2e10eed southbridge/amd/sr5650/sr5650.c: Fix bitwise logic and mask in loop
Correct mask to select bits 4-6 inclusively as per comment and use
bitwise operations while working with bits. Be sure to write back out
the data on the retrain.

See:
 commit cab9efb2 southbridge/amd/rsXY0/cmn.c: Fix bitwise logic and mask in loop

Change-Id: I95d1799514157b7849f3e473837aaf2fd9bd59b9
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7692
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2014-12-09 09:03:22 +01:00
Edward O'Callaghan b3b79afd55 mainboard/{iwill,amd/serenget_*}: Fix ptr discards const qualifier
Change-Id: I22e55eb2b7fe06c416e5e4fd322045bc7031ed63
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7693
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-12-09 06:13:47 +01:00
Martin Roth 48a243b16e utils: Remove references to tracker from manpages
abuild, inteltool, and superiotool's manpages still referenced reporting
bugs to tracker.coreboot.org.  Remove that url and change the message
to point to the coreboot mailing list instead.

Change-Id: I7a85bc2b36ccdb7f3798a39a08345c1a02a67e65
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7712
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-09 03:02:56 +01:00
Martin Roth a0a71b046a fsp platfoms: add prototype & consolidate main entry-point
- In '-ffreestanding' main() is just as any other function and so
it needs a type-signature. Fixes a clang warning.

- Bay Trail and Rangeley have the updated romstage.c with the code
moved into the chipset, put the prototype in romstage.c.

- The sandybridge code has not been updated, so the prototype
for it goes into chipset_fsp_util.h, next to the prototype for
romstage_main_continue.

- Correct the return value of baytrail main() from void * to void
and remove the unnecessary asmlinkage tag. I'm surprised that this
didn't generate a warning...

Change-Id: I85ac0797d1e55d2b7ffdca039a52820d7827e704
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7724
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-12-09 03:02:39 +01:00
Dave Frodin c43bce57f7 mainboard/gizmosphere/gizmo2: Start adding new mainboard
This is a direct copy of the amd/olivehill mainboard which
will be the starting point for this port.

Change-Id: I6a643f7ac35d89e21df0ffdf4e61a2da46e19b82
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/7721
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-12-09 00:03:06 +01:00
Edward O'Callaghan 7c0ee48510 drivers/intel/fsp/fsp_util.c: Remove attribute,optimize("O0")
This is not actually required. Tested on 'minnow max' hardware as
well as compared the asm of the optimized and non-optimized. Thanks Martin!

Change-Id: I06e71876c3a3a15101013623797c2ebbf449756d
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Found-by: Clang
Reviewed-on: http://review.coreboot.org/7694
Reviewed-by: Martin Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-12-08 18:27:21 +01:00
Dave Frodin 3ff4f85ccd northbridge/amd: Add the audio device to the PCI devices
Change-Id: I826f98e450c9a614930a5e83c7c6bfb4ccdc5984
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/7630
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2014-12-08 18:05:13 +01:00
Edward O'Callaghan 698dc74eba mainboard: Fix correct index variable usage in double loop construct
Change-Id: I672c532c3f7179038d41f269bba434b8703e254b
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Found-by: Clang
Reviewed-on: http://review.coreboot.org/7718
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-12-08 17:59:19 +01:00
Patrick Georgi b713d93525 edid: fill reserved bits fields in cb_framebuffer
If it's a 4 byte format (as per documentation), there
are some reserved bits, so let's mark them as such...

Change-Id: I50f12cfff2c9bb9d082a5f3c3ac54c0d514d862b
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/7674
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-12-08 10:48:32 +01:00
Edward O'Callaghan a3a722c5fc mainboard/siemens/sitemp_g1p1/mainboard.c: Remove unicode in string
Remove illegal character encoding in string literal.

Change-Id: I3c8dc67363705a2160e8266d1cea78c0d34d076f
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7713
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-08 09:40:23 +01:00
Edward O'Callaghan 5d0601767f vendorcode/amd/agesa/fam10: Build as a static library
Following the same reasoning as commit
 ee905a8 vendorcode/amd/agesa/fam15tn: Build as a static library
Since AGESA is stage-independent, we can build it just once, and use
the resulting static library in both rom and ram stages.

Change-Id: I8fbb318daacf64a14a71022705eb040a01c34fa8
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7699
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-08 06:24:18 +01:00
Edward O'Callaghan fd1349bb49 vendorcode/amd/agesa/fam15: Build as a static library
Following the same reasoning as commit
ee905a8 vendorcode/amd/agesa/fam15tn: Build as a static library
Since AGESA is stage-independent, we can build it just once, and use
the resulting static library in both rom and ram stages.

Change-Id: I7798b689db3e582649eb4af4ccd1877bb1d49063
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7698
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-08 06:24:08 +01:00
Martin Roth 99a3bba171 intel/baytrail: Spelling fixes
Change-Id: Ideb58634a029d55746421ad1ea4b80811bca403c
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7705
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-08 05:40:24 +01:00
Martin Roth 7c96629e94 intel/fsp_baytrail: Spelling fixes
Change-Id: Ica9e3a91718a7e490ff80e5029fc29650355eb47
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7704
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-08 05:40:01 +01:00
Martin Roth 1fc2ba5e6d samsung/exynos5420: Spelling Fixes
Change-Id: I966645c83ae78943a7dbb9dc05af4fded6f4e5b5
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7703
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-08 05:39:07 +01:00
Martin Roth de7ed6fc7c intel/broadwell: Spelling fixes
Change-Id: I2f970c6970b4996fcefbde89332210f5a1afe836
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7702
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-08 05:38:54 +01:00
Edward O'Callaghan 8ff0ead081 vendorcode/amd/agesa/f1{5,5tn,6kb}: Silence empty loop warn
Add decorations to specify that empty loop is intended so.

Change-Id: Ia3e40d341eca5e26da3832edc733cf1ccc96c136
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Found-by: Clang
Reviewed-on: http://review.coreboot.org/7688
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-07 22:36:39 +01:00
Edward O'Callaghan d189085b3f mainboard/google/samus: Fix usage of GNU field designator ext
Following the reasoning in,
 8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension

In C99 we defined a syntax for this. GCC's old syntax was deprecated.

Change-Id: Id3b16872f62660393d938d6f95977a4e3842d0d1
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7690
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-07 21:31:04 +01:00
Edward O'Callaghan fc3643f326 southbridge/dmp/vortex86ex/southbridge.c: Silence bitwise op warns
Silence some useless Clang warns in this case.

Change-Id: I202a85f7dec52c65d80e2bc56f7d9e4eb3e61d48
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7696
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-12-07 21:11:58 +01:00
Vladimir Serbinenko 318e481e55 Kconfig: Remove ACPI_SSDTX_NUM.
Its scope is limited to a single mainboard and is only to go through ifdef.
Kill it and move the value to the code.

Change-Id: I76a87e2790d57dee8f37b51e33d0689fffd3a59d
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7135
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-07 21:06:34 +01:00
Vladimir Serbinenko dc3d5ed3cb ga-b75m-d3h: Remove duplicate sata_port_map
Change-Id: I128f1dfea013a4f94c5b006a90c10aa32563d81c
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7691
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-12-07 17:16:16 +01:00
Vladimir Serbinenko 0fa7ac76bd vx800/vga.c: Remove extraneous parentheses.
Change-Id: Ic81b5f66871ec78c72f2adc5723f22fa94a672e8
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7682
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-12-07 15:51:15 +01:00
Vladimir Serbinenko daf7680805 via/vx900: Plumber registered DIMM to right place.
Currently due to enum mistake DDR3 = 0xb was confused with DIMM type and
interpreted as LRDIMM, considered unregistered and so every RAM was
unregistered.
Registered RAM is rarely used, so I suppose the code was never tested with them.
For unregistered RAM exactly the same codepath is followed.

Change-Id: I02fe8b1fd7be3bd382399ffa0eb513965a2a6d77
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7687
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-12-07 15:18:48 +01:00
Vladimir Serbinenko 0e675f72da ddr3: Plumber DIMM type to parsed structure.
Useful for distinguishing registered modules.

Change-Id: Ibf4a0f2cde6d50a1c5c1da0f50e3022a2bc7ccd7
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7686
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-12-07 15:18:41 +01:00
Alexandru Gagniuc 76c256134f hp/pavilion_m6_1035dx: select NO_UART_ON_SUPERIO in Kconfig
Change-Id: I324cdaf2025898b74bfc0d40c5ed8b88d2be5ad4
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7679
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-12-07 14:36:51 +01:00
Vladimir Serbinenko 5235cd085a x200/devicetree: Remove extraneous eventc.
Change-Id: If72daed326216e24da85a6a9d342f36f4e1d9de5
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7685
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-12-07 14:27:00 +01:00
Vladimir Serbinenko 1a3ee668c7 x200/romstage: Add missing include.
Change-Id: I47aa8619ba1e1939707ec654ffb54cae316929cf
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7684
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-12-07 14:01:56 +01:00
Vladimir Serbinenko 25fc532838 nehalem/raminit: Add decorations to specify that empty loop is intended so.
Change-Id: I6a05683daa6105e26017d1abf45881a9ef93ea30
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7683
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-12-07 14:01:43 +01:00
Vladimir Serbinenko 8e688b3d74 vx800: Silence clang warnings.
I have no such board to check the real fixes but this board shouldn't block
benefits for the rest of the tree.

Change-Id: I9e9d4af1b360bcf0099ac2901b08f7fcd7569097
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7681
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-07 14:01:28 +01:00
Vladimir Serbinenko 29b8a0976f early_me_native.c: Remove unused pci_write_dword_ptr.
Change-Id: I97f4ef373c250665c4a2265571e71a27ecef13da
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7680
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-07 12:55:48 +01:00
Vladimir Serbinenko ecbfa28c11 lenovo: Remove duplicate devicetree.cb eventc entry.
Keep only the last one: it was the one which was really used.

Change-Id: I19132f6224d6847e615e3c582aaa6e66b0d56c7a
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7677
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-07 11:48:27 +01:00
Edward O'Callaghan f0101a4f5a vendorcode/amd/agesa/f15tn/*/F15TnMsrTables.c: Topology Extensions Support
Topology Extensions Support (bit 54 of 0xC0011005) applies to
PACKAGE_TYPE_FS1r2 also. Rids us of:

 "Re-enabling disabled Topology Extensions Support"

showing up in dmesg.

Change-Id: Id123fa9632936c150cf1aebc4d34b404a4398ead
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7671
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2014-12-07 04:59:19 +01:00
Vladimir Serbinenko c746dcbe91 kontron/986lcd-m: Fix PCI interrupt routing.
The current interrupt routing shares interrupt 5 between LPC and PCI which
isn't possible.

Use IRQ 11 for all devices in PCI mode. Move conflicting LPC to free IRQ.

Change-Id: I3ac8c2f19195ef6b07f4ee7dde64dd038d024126
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7477
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-06 21:35:32 +01:00
Vladimir Serbinenko 845e17c3f7 Remove IRQ_SLOT_COUNT on all boards without PIRQ table.
This config is used only to generate PIRQ table. If no such table is
supplied there is no need for config.

Change-Id: I537d440f53019a6bf7f190446074e75e7420545a
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7566
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-12-06 21:34:19 +01:00
Alexandru Gagniuc 45b64fbf9d vendorcode/amd/agesa: Remove unused helper.c file
The contents of these files were guarded by a check for the _MSC_VER
macro, which we don't use.

Change-Id: Ic595c8e6284c54e1449cf21e0cebee8c9ce7c682
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7670
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-12-06 17:09:06 +01:00
Edward O'Callaghan 63ebb24c17 vendorcode/amd/agesa: Make Porting.h common between families
Change-Id: Ica17b2452498f30b710533caf610c9f0c1a0452c
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7594
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-12-06 11:39:42 +01:00
Edward O'Callaghan 4568f19d1f northbridge/intel/*/acpi/igd.asl: Trivial indent style fix
Change-Id: I26e92645264c69bbc032b0e7e44d7d31de2dfa4d
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7665
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-06 10:03:30 +01:00
Edward O'Callaghan 0a0d04895f soc/qualcomm/ipq806x/Kconfig: Fix indent style
Change-Id: I72c9c1f5811fafaeec9572b05726d5677e2c28b1
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7669
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-06 10:03:05 +01:00
Edward O'Callaghan d2344d03e2 sb/amd/agesa/hudson/: Don't include IMC and XHCI blobs by default
Don't build in non-essential blobs by default. However, if the user
selected to use the blobs repository, then default to including the
blobs.

Change-Id: Ie90f00d7c18d725f24fe1503fadaf098d3cefa4a
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7638
Tested-by: build bot (Jenkins)
2014-12-06 09:29:43 +01:00
Edward O'Callaghan c9e7dc138d mainboard/lenovo/g505s/Kconfig: Has no SuperIO
Change-Id: I30fdfb70506241838436c3afbf6ddfdbff5cb302
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7668
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-12-06 08:01:35 +01:00
Edward O'Callaghan a23036c8d8 mainboard/lenovo/g505s: Build in EC ASL support for KBD/AUX ports
Rather than have Linux report:
 i8042: PNP: No PS/2 controller found. Probing directly.
and go off probing PNP config space, build in EC ASL for the
PS/2 keyboard and mouse.

The ASL explicitly passes these resources to the Linux to avoid
said probe.

ASL Details:
 PS/2 keyboard (PNP0303 at 0x60,0x64 irq 1 )
 PS/2 mouse    (PNP0F13 at 0x60,0x64 irq 12)

Change-Id: I0697fab65915907fbe2b3551182b3a1b0d665ddb
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7651
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-06 07:39:58 +01:00
Edward O'Callaghan 05a1dc3c44 ec/compal/ene932/acpi/superio.asl: Provide PNP0F13 AUX ASL
Provide ASL to support the AUX port (a.k.a Mouse) found at
0x60,0x64 irq 12 on this EC.

Change-Id: I6969ae4d492570136a8e14e42509638857e1ed85
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7650
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-12-06 07:39:41 +01:00
Edward O'Callaghan 14581fc632 mainboard/lenovo/g505s: Toggle on IOMMU support
Toggle on in devicetree.cb and build into AGESA by buildOpts.c.
Add ACPI and MPTABLES interrupt routers for IOMMU also.

Change-Id: Ia838f9b70f09ed1180daeb5382edc08c4b74946c
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7643
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-06 07:39:26 +01:00
Edward O'Callaghan e2b15d569a vendorcode/amd/agesa/f15tn: Fix GnbIommuScratch in AGESA compilation
Missing IOMMU support is missing from the libagesa Makefile, it also
lacks a header with type-signature and a few bad typecast issues.

Change-Id: I7f2ad2104de9baaa66dbb6ffeb0f2b4d35fa5c16
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Co-Author: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/7642
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-06 07:38:54 +01:00
Edward O'Callaghan f5c463f5e6 mainboard/*/acpi/superio.asl: Use non-local inclusion syntax
Use non-local inclusion syntax over relative paths for
'drivers/pc80/ps2_controller.asl'.

Change-Id: Ie2bfa893dc268ec5118d2a9addadbc759d85d357
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7664
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-12-06 05:57:55 +01:00
Alexandru Gagniuc 986349df64 vendorcode/amd/agesa/fam15tn: Clean #includes in public headers
Right now, coreboot code using AGESA headers can only build if all the
AGESA path are given to the compiler via the "-I" option. This is sub-
optimal, as it requires us to have every AGESA source directory
specified as a compiler include path. This pollutes our global include
paths.

We restrict the compiler include paths to only allow "AGESA_ROOT/" and
"AGESA_ROOT/Include". We then modify the AGESA headers to specify
non-local include files relative to "AGESA_ROOT/Include".

We use the convention that includes relative to the directory of the
header are included as "path/to/header.h", while includes relative to
AGESA_ROOT are included as <path/to/header.h>.

This change allows building coreboot code based on AGESA with the
limited subset of include paths, but does not allow AGESA itself to
build with this restricted subset.

Change-Id: I31102273c8caa8d6b1d80774bfd35711825bec03
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5424
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-12-06 05:43:20 +01:00
Edward O'Callaghan c5c21d3fe1 mainboard/lenovo/g505s/buildOpts.c: Trivial variable rename
Minor fix to avoid confusion, nothing to see here.

Change-Id: I89d56a91d2df049e85cf49c23218620caba84880
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7654
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-06 03:25:52 +01:00
Martin Roth 14ca52bb96 fsp_baytrail: Allow selection of USB controller by get_option
It was requested to be able to update XHCI vs EHCI via get_option,
so I've added it here for minnow max.  This could get moved to the
chipset_fsp_util.c file later, but I'm adding it here for now.

More checking needs to be added to this:
- Are both controllers enabled in devicetree?  If not, we don't want
to allow the switch.

Change-Id: I4d8d2229cb9fa0cd9068701454b28ffac6d8e767
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7633
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-12-06 03:23:19 +01:00
Martin Roth cf52f9761f intel/minnowmax: Update devicetree
- Align register values.

- Enable both EHCI and XHCI so the choice of port used can be made
at runtime.  When both are enabled in devicetree, XHCI currently gets
disabled by the FSP chipset code.  This can be overridden in mainboard
code or by a Kconfig entry, but there's a question about whether or not
that's desired.

- Enable function 1c.0 so the rest of the functions will be
seen, even though the function is not actually used.  This is a
short-term fix, as the correct solution is to determine whether or not
any of the other functions are enabled, and not to hide function 0 if
they are.  I am working on that, but I want to get this in for now.

Change-Id: I83ae12c2393024b82a55d0b3a5ffa8782e16107e
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7663
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-12-06 03:14:02 +01:00
Alexandru Gagniuc d2e5f6815e southbridge/hudson: Disable USB controllers if devicetree says so
Change-Id: I009a01d3324d48d2eeda87d74c8e3e7c27958ee2
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5525
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-06 02:47:18 +01:00