Add 'pci_map_bus' function and PCIE_MEDIATEK config for MediaTek
platform.
TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
== NVME IDENTIFY CONTROLLER DATA ==
PCI VID : 0x15b7
PCI SSVID : 0x15b7
SN : 21517J440114
MN : WDC PC SN530 SDBPTPZ-256G-1006
RAB : 0x4
AERL : 0x7
SQES : 0x66
CQES : 0x44
NN : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006
BUG=b:178565024
BRANCH=cherry
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: I9ea7d111fed6b816fa2352fe93c268116519a577
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Move the common APIs to pci_ops.c and IO based operations to
pci_io_ops.c, and add pci_map_bus_ops.c to support bus mapping.
TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
== NVME IDENTIFY CONTROLLER DATA ==
PCI VID : 0x15b7
PCI SSVID : 0x15b7
SN : 21517J440114
MN : WDC PC SN530 SDBPTPZ-256G-1006
RAB : 0x4
AERL : 0x7
SQES : 0x66
CQES : 0x44
NN : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006
BUG=b:178565024
BRANCH=cherry
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: Ie74801bd4f3de51cbb574e86cd9bb09931152554
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Add 'lb_fill_pcie' function to pass PCIe information from coreboot to
libpayload, and add CB_ERR_NOT_IMPLEMENTED to the cb_err enum for the
__weak function.
ARM platform usually does not have common address for PCIe to access the
configuration space of devices. Therefore, new API is added to pass the
base address of PCIe controller for payloads to access PCIe devices.
TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
== NVME IDENTIFY CONTROLLER DATA ==
PCI VID : 0x15b7
PCI SSVID : 0x15b7
SN : 21517J440114
MN : WDC PC SN530 SDBPTPZ-256G-1006
RAB : 0x4
AERL : 0x7
SQES : 0x66
CQES : 0x44
NN : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006
BUG=b:178565024
BRANCH=cherry
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: I6cdce21efc66aa441ec077e6fc1d5d1c6a9aafb0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
We wrote to the wrong register. The EN bit is in the CC (Controller
Configuration) register at 0x14.
Fixes re-initialization in QEMU and on siemens/chili during a second
FILO run.
Change-Id: I125de55d7f1a7c9f070437190c5a08a288b274f8
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
We only need to know if the NVMe command set is supported. Other
command-set bits can be set too, but we don't have to care.
Fixes init in QEMU which has more command-set bits set by now.
Change-Id: I29a693cf8cc13775e94dc671e8d0412ad86fef9c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
We mustn't try to release resources that we haven't acquired yet. Also,
sending commands to the NVMe device is futile if we already timed out.
Fixes hangs after a failed init noticed in QEMU and on siemens/chili.
Change-Id: Ib83c7785d6e0dc3c44fbd50a30694c74932750d6
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Replace 'struct lb_uint64' with 'typedef __aligned(4) uint64_t
lb_uint64_t', and remove unpack_lb64/pack_lb64 functions since it's no
longer needed.
Also replace 'struct cbuint64' with 'cb_uint64_t' and remove
'cb_unpack64' in libpayload for compatible with lb_uint64_t.
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: If6b037e4403a8000625f4a5fb8d20311fe76200a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
It looks like the u-root 'master' branch was renamed to 'main'.
Change-Id: I384ba66289a49bf226b505615bd16bdf85612c1a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62590
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
EDK_TOOLS_PATH is set on lines 85 and 137. Remove the instance
on 85. edk2 still builds correctly.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I0c837f14693941afec194b140c93d786ea784e53
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Move STRINGIFY() from coreboot string.h to commonlib/bsd/helpers.h
Remove redundant defines from libpayload.h and libpayloads' standard
headers.
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I3263b2aa7657759207bf6ffda750d839e741f99c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Include paths fixup macro for vboot was broken and was adding
unnecessary prefix to paths from $(coreboottop). This patch adds correct
filters to fix this behavior.
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I264e715fa879a4e56b6e5f5423916298e8780a2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Update iPXE stable from commit id ebf2eaf515:
Mar 18 10:24:08 2019 +0000
[intel] Add PCI ID for I219-V and -LM 6 to 9
to commit id 6ba671acd9:
Jan 17 16:17:17 2022 +0000
[efi] Attempt to fetch autoexec script via TFTP
This brings in 424 new commits and fixes the build with coreboot-sdk
2021-09-23_b0d87f753c.
TEST=Build PC Engines apu2 board and boot it over network with the
iPXE
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ide12a3a3082f9ea027e180518a80e6c0772b1232
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
SeaBIOS 1.16.0 was released on March 2nd. Thus, update the stable
version from 1.14.0 to 1.16.0.
Change-Id: I475a9be47171bfbe3b3c2d4d1d14bb753d8575a8
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add prompt to Boot Timeout so that it can be easily configured
from a config file.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I62b8f0a9b5bc0796506b991199a457d6b34ae494
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
cb_err_t was meant to be used in place of `enum cb_err` in all
situations, but the choice to use a typedef here seems to be
controversial. We should not be arbitrarily using two different
identifiers for the same thing across the codebase, so since there are
no use cases for serializing enum cb_err at the moment (which would be
the primary reason to typedef a fixed-width integer instead), remove
cb_err_t again for now.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Iaec36210d129db26d51f0a105d3de070c03b686b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
coreboot recently introduced non-printable loglevel markers in the CBMEM
console. Payloads were generally unaffected since they don't use log
levels and it is still legal to append lines without a marker to the
log. However, payloads using cbmem_console_snapshot() to display
existing logs from coreboot have started seeing '?' characters in place
of the markers. This patch fixes the issue by filtering out marker
characters.
BUG=b:221909874
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I4a9e5d464508320cf43ea572d62896d38c2a128d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
TPM1_MODE and TPM2_MODE defines have to be added to vboot and payload
cflags to make them build correctly without requiring payloads to provide
defines.
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I567a9f04d7089699840dc7e0a063cf3030fb934b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Convert BMP to the correct format at build time, which removes the
requirement for any runtime checks.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I4f1e9c8df2ca7d66f362f9fa5688d6cb443c2581
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
By default, edk2 allows 1000000μs for SD Card Readers and eMMC to
initialize which is excessive and causes a boot delay. This makes
the value configurable and uses a default of 1000μs which is sufficient
for the majority of readers. The value of 1000μs was hardcoded in
MrChromeBox's fork for around 2 years with no reported issues.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I873bcddf6f37a9eaae5c84991b3996d51fb460d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Add TIANOCORE_PRIORITIZE_INTERNAL which, when enabled, will build edk2
with boot from internal devices before external devices.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ib1f73c8f3f2f2376cdc197b58d259446dc5f0138
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add TIANOCORE_HAVE_EFI_SHELL, which when enabled, will build edk2
with the EFI Shell binary.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I1272f514e3f5becfe1fddd58ca0d820c5d1c1b54
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Adds TIANOCORE_FOLLOW_BGRT_SPEC which, when enabled, will follow
the BGRT Specification implemented by Microsoft and the Boot Logo
will be vertically centered 38.2% from the top of the display.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: If508166fe657d1cc032dd09a0fa231c7b60d9846
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add TIANOCORE_BOOT_MANAGER_ESCAPE which, when enabled, will use
Escape as the hot-key to access the Boot Manager. This replaces
the default key of F2.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I1e60d116367542f55f0ffa241a6132e4faabe446
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61757
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
To be able to link libcbfs without vboot, we need garbage
collection now.
Change-Id: Id9a9fe7efb9fb4409a43ae8357f4f683618805d2
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Casts from integer to pointer are usually a case for phys_to_virt().
Change-Id: I861d435ff2361cdc26a2abd46d43b9346fa67ccc
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Rework edkii makefile so that the various build options are
unified between CorebootPayloadPkg, uefipayload_202107 and
upstream.
This sets the project directory based on the git repository name
i.e. https://github.com/mrchromebox/edk2 becomes mrchomebox
Also builds to $(obj)/UEFIPAYLOAD.fd and allows using a commit
ID without a branch.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I3cc274e7385dd71c2aae315162cc48444b7eaa5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Martin Roth - Personal <martinroth@google.com>
Lack of strip made it required to pass arguments to the
kconfig-to-binary macro without spaces. Strip fixed invalid behavior of
this macro.
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I9889b45f773b9675fae287086d324c180c505a4b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Add an option to build skiboot as a payload. This makes QEMU Power9
board simpler to use as skiboot is necessary anyway.
Change-Id: I0b49ea7464c97cc2ff0d5030629deed549851372
Signed-off-by: Igor Bagnucki <igor.bagnucki@3mdeb.com>
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
CBFS MCache size was assigned a value of the coreboot tables entry size
instead of the MCache size.
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I8a8c3a10c6032121b4c5246d53d2643742968c09
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Don't assume that libpayload is built from a fully checked
out coreboot tree.
There's already an override when building vboot, so reuse
that override when referring to its header files.
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Change-Id: I503c69a593dd68b3a974fbdbb64d7bb25d6c7f63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Rob Barnes <robbarnes@google.com>
This reverts commit 2a8de6dafb.
SeaBIOS 1.15.0 regresses on systems with NVMe devices [1]:
> Greetings! Was this patch set tested on bare metal hardware? I'm
> seeing "GRUB loading: Read Error" when attempting to boot from NVMe on
> various Purism Librem devices (Intel Skylake thru Cometlake hardware).
> Reverting this series resolves the issue.
So, revert back to SeaBIOS 1.14.0.
[1]: https://mail.coreboot.org/hyperkitty/list/seabios@seabios.org/message/SRECAGH4NE3XPDWJ2YI526L5LPSJWENJ/
Change-Id: If2ec738d478f11b203f499eaa28197357de6630d
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61179
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
llvm-ar does not support "open" script command, and fails with an error.
This patch fixes it by removing lines `$(AR) rc <object-files>` and
it puts them as "addmod" commands. This way all object files and
archives can be packed into one archive.
Change-Id: I0c53d1d613b5edc321e268d1d996fac3146680f8
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
New CBFS API uses commonlib/bsd/cbfs_serialized.h, which includes
vboot's vb2_sha.h. And, because vboot's includes are not available
in libpayload's installation directory nor in lpgcc paths, it was
causing compilation errors. This patch fixes this issue.
lpgcc will look for `vboot` directory like it is doing for `include`
directory to create correct paths. However, if payload will be built
using libpayload's build dir as a base, then vboot headers from
3rdparty/vboot will be used, as there is no way to pass VBOOT_SOURCE
from makefile to lpgcc.
Moreover, this patch moves VBOOT_SOURCE to the main Makefile to
make it available for installation target, to install headers from
vboot directory provided by caller.
Change-Id: I68dd7e1545cfcaf24547d8a9fe289447c79da222
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reported-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61032
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The goal when adding the new CBFS API in CB:59497 was that the old CBFS
code would be left completely untouched and just moved to the side a
bit, so that it could continue to work for the payloads that use it
until they all have time to transition to the new CBFS API.
Unfortunately, between the different iterations of the patch something
went wrong with that and the final committed version of cbfs_legacy.c
does differ in some parts from the original code, including a changed
macro definition that breaks decompression support. This patch restores
all the legacy CBFS files to exactly what they used to be (other than
the necessary changes in cbfs_core.h to avoid double definition
clashes).
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ic7fd428acb03d3830f66f807cd1d7cdbd652f409
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
CBFS_VERIFICATION was depending on the VBOOT instead of on VBOOT_LIB,
which made enabling CBFS_VERIFICATION impossible. VBOOT is not
available, like in the main coreboot, but is was changed to VBOOT_LIB,
and was not correctly adjusted in patch instroducing CBFS_VERIFICAITON
option.
Change-Id: Ie23bad5f0ed3faf17a2ed7a3ad99310ee803edd2
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This patch introduces equivalents of unverified_area CBFS access
functions added to the main coreboot tree in CB:59678
Change-Id: Ibadfd2a5cb6ad037ef1222b0a4301f90a79a127b
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit adds new CBFS API, which is based on the one available in
the main coreboot source tree. Libpayload implementation supports RO/RW
file lookups and file contents verification.
Change-Id: I00da0658dbac0cddf92ad55611def947932d23c7
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This patch introduces building and linking of 3rdparty/vboot with
libpayload. VBoot can be enabled by setting CONFIG_LP_VBOOT_LIB.
Moreover it can be configured to use either TPM or TPM 2.0 mode,
and whether to use SHA256 processor extension instructions on x86.
Change-Id: I2d9d766a461edaa0081041c020ecf580fd2ca64e
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60080
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Writing a coreboot image without a payload to a board's flash chip will
result in a non-bootable system, so warn the user if this is the case.
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Change-Id: I15ae9548a45e9f566c84db41e8e171c6bc179057
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Jianjun Wang